United Microelectronics Corp.

Marlin Semiconductor Limited

Chun-Chia Chen

Yao-Jhan Wang

Te-Chang Hsu

Chung-Fu Chang

Chun-Tsen Lu

Kuan-Hung Chen

Guang-Yu Lo

Shih-Chieh Hsu

Chun-Jen Huang

Chi-Horn Pai

Zen-Jay Tsai

Ying-Hung Chou

Yi-Chung Sheng

Chih-Wei Yang

Tsai-Fu Chen

Ta-Kang Lo

Shao-Hua Hsu

Chih-Chung Chen

Hung-Chang Chang

Shang-Jr Chen

Shih-Hao Su

Shuo-Lin Hsu

Hsin-Ta Hsieh

Chen-Chien Li

Ying-Hsien Chen

A semiconductor device includes a gate structure on a substrate, an offset spacer adjacent to the gate structure, a main spacer around the offset spacer, a source/drain region adjacent to two sides of the main spacer, a contact etch stop layer (CESL) adjacent to the main spacer, and an interlayer dielectric (ILD) layer around the CESL. Preferably, a dielectric constant of the offset spacer is higher than a dielectric constant of the main spacer.

Semiconductor device and method for fabricating the same

A method for fabricating semiconductor device includes the steps of: forming a fin-shaped structure on a substrate; forming a gate dielectric layer on the fin-shaped structure; forming a gate electrode on the fin-shaped structure; performing a nitridation process to implant ions into the gate dielectric layer adjacent to two sides of the gate electrode; and forming an epitaxial layer adjacent to two sides of the gate electrode.

A method for fabricating semiconductor device includes the steps of: forming a gate structure on a substrate; forming a spacer around the gate structure; forming a first contact etch stop layer (CESL) around the spacer; forming a mask layer on the first CESL; removing part of the mask layer; removing part of the first CESL; forming a second CESL on the mask layer and the gate structure; and removing part of the second CESL.

Method for fabricating a metal gate transistor with a stacked double sidewall spacer structure

Metal gate transistor with a stacked double sidewall spacer structure

A method for fabricating semiconductor device includes the steps of first forming a gate structure on a substrate, forming a contact etch stop layer (CESL) on the gate structure, forming an interlayer dielectric (ILD) layer around the gate structure, performing a curing process so that an oxygen concentration of the CESL is different from the oxygen concentration of the ILD layer, and then performing a replacement metal gate process (RMG) process to transform the gate structure into a metal gate.

A method for fabricating a semiconductor device. After forming SiGe epitaxial layer within the Core_p region, the hard mask is removed. A contact etch stop layer (CESL) is deposited on the composite spacer structure and the epitaxial layer. An ILD layer is deposited on the CESL. The ILD layer is polished to expose a top surface of the dummy gate. The dummy gate and a first portion of the first nitride-containing layer of the composite spacer structure are removed, thereby forming a gate trench and exposing the first gate dielectric layer. The first gate dielectric layer is removed from the gate trench, and a second portion of the first nitride-containing layer and the oxide layer are removed from the composite spacer structure, while leaving the second nitride-containing layer intact.

Method for fabricating metal replacement gate semiconductor device using dummy gate and composite spacer structure

A fabricating method of a semiconductor structure includes providing a substrate divided into a dense region and an isolated region, wherein a first gate structure is disposed within the dense region, and a second gate structure is disposed within the isolated region. Then, a first material layer is formed to cover the first gate structure, the second gate structure and the substrate. Later, a second material layer is formed to cover the first material layer. After that, the second material layer within the dense region is entirely removed. Subsequently, a third material layer is formed to cover the isolated region and the dense region. Next, the substrate is etched to forma first recess at two sides of the first gate structure, and a second recess at two sides of the second gate structure. Finally, an epitaxial layer is formed to fill the first recess and the second recess.

Fabricating method of a semiconductor structure with an epitaxial layer

A manufacturing method of a semiconductor device includes the following steps. A first gate dielectric layer is formed in a first gate trench and a second gate dielectric layer is formed in a second gate trench. A first bottom barrier layer is formed on the first gate dielectric layer and the second gate dielectric layer. A first conductivity type work function layer is formed on the first bottom barrier layer. A first treatment to the first gate dielectric layer and/or a second treatment to the first bottom barrier layer on the first gate dielectric layer are performed before the step of forming the first conductivity type work function layer. The first treatment and the second treatment are used to modify threshold voltages of specific transistors, and thicknesses of work function layers formed subsequently may be modified for increasing the related process window accordingly.

Manufacturing method of semiconductor device

A method for fabricating a semiconductor device is described. A gate layer, a C-doped first protective layer and a hard mask layer are formed on a substrate and then patterned to form a first stack in a first area and a second stack in a second area. A second protective layer is formed on the sidewalls of the first and the second stacks. A blocking layer is formed in the first area and a first spacer formed on the sidewall of the second protective layers on the sidewall of the second stack in the second area. A semiconductor compound is formed in the substrate beside the first spacer. The blocking layer and the first spacer are removed. The hard mask layer in the first stack and the second stack is removed.

Method for fabricating semiconductor device and PMOS device fabricated by the method

A method of manufacturing a CMOS device includes providing a substrate having a first region and a second region; forming a first gate structure and a second gate structure, each of the gate structures comprising a sacrificial layer and a hard mask layer; forming a patterned first protecting layer covering the first region and a first spacer on sidewalls of the second gate structure; performing an etching process to form first recesses in the substrate; performing a SEG process to form epitaxial silicon layers in each first recess; forming a patterned second protecting layer covering the second region; and performing a dry etching process with the patterned second protecting layer serving as an etching mask to etch back the patterned first protecting layer to form a second spacer on sidewalls of the first gate structure and to thin down the hard mask layer on the first gate structure.

Growing community of inventors

Tainan, Taiwan

Chun-Chia Chen