Realtek Semiconductor Inc.

Chun-chi Yu

Chih-wei Chang

Fu-chin Tsai

Ger-Chih Chou

Shih-Chang Chen

Chih-Wei Chang

Kuo-Wei Chi

Gerchih Chou

Min-Han Tsai

Shih-han Lin

Ger-chih Chou

The present disclosure discloses a memory access interface device. A clock generation circuit generates reference signals. A transmitter transmits an output command and address signal to a memory device according to the reference signals. A signal training circuit executes a training process in a training mode that includes steps outlined below. A training signal is generated such that the training signal is transmitted as the output command and address signal. The training signal and the data signal generated by the memory device are compared to generate a comparison result indicating whether the data signal matches the training signal. The comparison result is stored. The clock generation circuit is controlled to modify a phase of at least one of the reference signals to be one of a plurality of under-test phases to execute a new loop of the training process until all the under-test phases are trained.

Memory system, memory access interface device and operation method thereof

A physical layer (PHY) circuit, a write leveling training circuit and a method for calibrating an access control signal are provided. The PHY circuit includes the write leveling training circuit, a clock generator and a transmitting (TX) logic. The write leveling training circuit generates at least one phase control signal. The clock generator outputs at least one control clock according to the phase control signal. The TX logic generates the access control signal according to the control clock, wherein a phase of the access control signal is associated with the phase control signal. The memory device outputs a data signal according to a phase error between a memory clock and the access control signal, and the write leveling training circuit determines a target value of the phase control signal according to the data signal, in order to minimize the phase error between the memory clock and the access control signal.

Physical layer circuit, write leveling training circuit and method for calibrating access control signal transmitted to memory device

The present disclosure discloses a memory access interface device. A clock generation circuit generates reference clock signals. Each of access signal transmission circuits each includes a duty cycle adjusting circuit, a duty cycle detection circuit, a frequency division circuit and an asynchronous first-in-first-out circuit. The duty cycle adjusting circuit performs duty cycle adjustment on one of the reference clock signals according to a duty cycle detection signal to generate an output clock signal having a duty cycle. The duty cycle detection circuit detects a variation of the duty cycle to generate the duty cycle detection signal. The frequency division circuit divides a frequency of the output clock signal to generate a read clock signal. The asynchronous first-in-first-out circuit receives an access signal from a memory access controller and outputs an output access signal according to the read clock signal to access the memory device accordingly.

Memory system and memory access interface device thereof for supporting different speed modes

A method for calibrating a data reception window includes: (A) setting a level of a reference voltage by different predetermined values and repeatedly sampling a data signal to obtain multiple first valid data reception windows; (B) establishing a first eye diagram based on the first valid data reception windows; (C) resetting the level of the reference voltage by the predetermined values combined with a first offset and repeatedly sampling the data signal according to the reference voltage to obtain multiple second valid data reception windows and (D) selectively updating the first eye diagram according to the second valid data reception windows. When width of a second valid data reception window is greater than width of a first valid data reception window corresponding to the same predetermined value, the first valid data reception window in the first eye diagram is replaced by the second valid data reception window.

Memory controller and method for calibrating data reception window

A test method for a delay circuit and a test circuitry are provided. The test circuitry incudes the delay circuit that essentially includes multiple serially connected logic gates, a clock pulse generator at an input end of the delay circuit for generating one or more cycles of clock signals, and a counter at an output end of the delay circuit for counting the clock signals passing through the delay circuit. The test circuitry implements a test mode by switching lines to the clock pulse generator and the counter. The test circuitry relies on a comparison result of a counting result made by the counter and a number of the cycles of the clock signals to test any failure of the delay circuit.

Test method for delay circuit and test circuitry

An eye diagram measuring method includes: sampling a compensated input signal according to a reference voltage and a reference clock to obtain a first sampling result; and sampling a to-be-compensated input signal according to a scan voltage and a scan clock to obtain a second sampling result, including: (b1) storing a minimum phase and a voltage level which render the first sampling result identical to the second sampling result; (b2) increasing the voltage level and repeating operation (b1); (b3) decreasing the voltage level and repeating operation (b1); (b4) storing a maximum phase and the voltage level which render the first sampling result identical to the second sampling result; (b5) increasing the voltage level and repeating operation (b4); and (b6) decreasing the voltage level and repeating operation (b4). Voltage levels, maximum phases and minimum phases that are stored are for adjusting the reference voltage and the reference clock.

Receiver of communication system and eye diagram measuring method

The present invention discloses a data transmission apparatus having clock gating mechanism. Each of data transmission circuits has a flip-flop depth of N and receives a write clock signal and one of read clock signals to receive and output one of data signals. A write clock gating circuit receives a write clock gating enabling signal to transmit the write clock signal to the data transmission circuits. Each of read clock gating circuits receives one of read clock gating enabling signals to transmit one of the read clock signals. The gating signal transmission circuit has a flip-flop depth of N+M and receives the write and the read clock signals to receive the write clock gating enabling signal and output the read clock gating enabling signals. A largest timing difference among the read clock signals is P clock cycles and M is at least ┌P┐.

Data transmission apparatus and method having clock gating mechanism

Disclosed is a DDR SDRAM signal calibration device capable of adapting to the variation of voltage and/or temperature. The device includes: an enablement signal setting circuit configured to generate data strobe (DQS) enablement setting; a signal gating circuit configured to generate a DQS enablement setting signal and a DQS enablement signal according to the DQS enablement setting and then output a gated DQS signal according to the DQS enablement signal and a DQS signal; and a calibration circuit configured to generate a first delay signal according to the DQS enablement setting signal and generate a second delay signal according to the first delay signal, the calibration circuit further configured to generate a calibration signal according to the first and second delay signals and the DQS signal. The enablement signal setting circuit maintains or adjusts the DQS enablement setting according to the calibration signal.

Growing community of inventors

HSINCHU, Taiwan

Chun-chi Yu