Dcg Systems Gmbh

Credence Systems Corporation

Nptest, Inc.

Schlumberger Technologies, Inc.

Chun-Cheng Tsao

Theodore R Lundquist

Erwan Le Roy

Eugene A Delenia

John Valliant

William B Thompson

Christian Boit

Rajesh Kumar Jain

Seema Somani

Peter Sadewater

Christopher Shaw

Uwe Jürgen Kerst

Steven A Kasapi

Stephan Schoemann

An optical coupling apparatus for a dual column charged particle beam tool allowing both optical imaging of an area of an integrated circuit, as well as localized heating of the integrated circuit to form silicide. In one embodiment, optical paths from a whitelight source and a laser source are coupled together by way of first and second beam splitters so that a single optical port of the dual column tool may be utilized for both imaging and heating. In another embodiment, a single laser source is employed to provide both illumination for standard microscopy-type imaging, as well as localized heating. In a third embodiment, a single laser source provides heating along with localized illumination for confocal scanning microscopy-type imaging.

Optical coupling apparatus for a dual column charged particle beam tool for imaging and forming silicide in a localized manner

An apparatus and method for processing an integrated circuit employing optical interference fringes. During processing, one or more wavelength lights are directed on the integrated circuit and based upon the detection of interference fringes and characteristics of the same, further processing may be controlled. One implementation involves charged particle beam processing of an integrated circuit as function of detection and/or characteristics of interference fringes. A charged particle beam trench milling operation is performed in or on the substrate of an integrated circuit. Light is directed on the floor of the trench. Interference fringes may be formed from the constructive or destructive interference between the light reflected from the floor and the light from the circuit structures. Resulting fringes will be a function, in part, of the thickness and/or profile of the trench floor. Milling may be controlled as a function of the detected fringe patterns.

Apparatus and method for optical interference fringe based integrated circuit processing

An apparatus and method for processing an integrated circuit employing optical interference fringes. During processing, light is directed on the integrated circuit and based upon the detection of interference fringes, further processing may be controlled. One implementation involves charged particle beam processing of an integrated circuit as function of detection of interference fringes. A charged particle beam trench milling operation is performed in or on the substrate of an integrated circuit. Light is directed on the floor of the trench. When the floor approaches the underlying circuit structures, some light is reflected from the floor of the trench and some light penetrates the substrate and is reflected off the underlying circuit structures. Interference fringes may be formed from the constructive or destructive interference between the light reflected from the floor and the light from the circuit structures. Processing may be controlled as function of the detection of interference fringes.

Localized trenches or access holes are milled in a semiconductor substrate to define access points to structures of an integrated circuit intended for circuit editing. A conductor is deposited, such as with a focused ion beam tool, in the access holes and a localized heat is applied to the conductor for silicide formation, especially at the boundary between a semiconductor structure, such as diffusion regions, and the deposited conductor. Localized heat may be generated at the target location through precise laser application, current generation through the target location, or a combination thereof.

Apparatus and method of forming silicide in a localized manner

An integrated FIB/PEM apparatus and method for performing failure analysis on integrated circuits. In-situ failure analysis is enabled by integrating Photon Emission Microscopy into a Focused Ion Beam system, thereby improving throughput and efficiency of Failure Analysis. An iterative method is described for identifying and localizing fault sites on the circuit.

Integration of photon emission microscope and focused ion beam

Methods and apparatus for integrated circuit diagnosis, characterization or modification using a focused ion beam. A method for editing an integrated circuit includes acquiring an image of structures of an integrated circuit by applying a focused ion beam to an outer surface of the integrated circuit to visualize structures beneath the outer surface of the integrated circuit. The method includes using the image to find a location of a circuit element in the integrated circuit and then performing one or more editing operations on the circuit element by applying a focused ion beam to the location found.

Imaging integrated circuits with focused ion beam

Apparatus and method for exposing a selected feature of an integrated circuit device such as a selected portion of the metallization layer, from the backside of the integrated circuit substrate without disturbing adjacent features of the device such as the active semiconductor regions. This is performed using an FIB (focused ion beam) etching process in conjunction with observation by an optical microscope to form a trench through the substrate. The process includes a precise optical endpointing technique to monitor the remaining thickness of the semiconductor substrate at the floor of the trench. It is important to terminate etching of the trench so that the trench floor extends as close to the active semiconductor structures as desired and yet is not detrimental to device operation. This is done without introducing a need for any additional tool. This is carried out using an infra-red optical technique which observes the interference fringes generated by the reflections from the silicon substrate surface and from semiconductor device circuitry layers to quantify the remaining semiconductor substrate thickness in the trench.

Method for determining thickness of a semiconductor substrate at the floor of a trench

A reliable, inexpensive 'back side' thinning process and apparatus therefor, capable of globally thinning an integrated circuit die to a target thickness of 10 microns, and maintaining a yield of at least 80%, for chip repair and/or failure analysis of the packaged die. The flip-chip packaged die is exposed at its backside and mounted on a lapping machine with the backside exposed. The thickness of the die is measured at at least five locations on the die. The lapping machine grinds the exposed surface of the die to a thickness somewhat greater than the target thickness. The exposed surface of the die is polished. The thickness of the die is again measured optically with high accuracy. Based on the thickness data collected, appropriate machine operating parameters for further grinding and polishing of the exposed surface are determined. Further grinding and polishing are performed. These steps are repeated until the target thickness is reached.

Method and apparatus for global die thinning and polishing of flip-chip packaged integrated circuits

Methods for integrated circuit diagnosis, characterization or modification using a charged particle beam. In one implementation, the bulk silicon substrate of an integrated circuit is thinned to about 1 to 3 &#x3bc;m from the deepest well, a voltage is applied to a circuit element that is beneath the outer surface of the thinned substrate. The applied voltage induces an electrical potential on the outer surface, which is detected as a surface feature on the outer surface by its interaction with the charged particle beam.

Measuring back-side voltage of an integrated circuit

A reliable, inexpensive &ldquo;back side&rdquo; thinning process, capable of globally thinning an integrated circuit die to a target thickness of 10 microns, and maintaining a yield of at least 80%, for chip repair and/or failure analysis of the packaged die. The flip-chip packaged die is exposed at its backside and mounted on a lapping machine with the backside exposed. The thickness of the die is measured at at least five locations on the die. The lapping machine grinds the exposed surface of the die to a thickness somewhat greater than the target thickness. The exposed surface of the die is polished. The thickness of the die is again measured optically with high accuracy. Based on the thickness data collected, appropriate machine operating parameters for further grinding and polishing of the exposed surface are determined. Further grinding and polishing are performed. These steps are repeated until the target thickness is reached.

Method for global die thinning and polishing of flip-chip packaged integrated circuits

A laser beam is used to probe an integrated circuit device under test. A single laser provides a single laser pulse which is divided into two pulses, both of which are incident upon the device under test. After the two pulses interact with the device under test, the two pulses are separated and detected by two photo detectors. The electrical signals output by the photo detectors are then subtracted, which cancels out any common mode noise induced on both pulses including noise due to mechanical vibration of the device under test and also any noise from the laser. The difference signal can be used to reproduce a time varying signal in the device under test.

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Cupertino, CA, United States of America

Chun-Cheng Tsao