Mediatek Corporation

Qisda Corporation

Chun-Cheng Liu

Zwei-Mei Lee

A comparator offset calibration system having a comparator offset evaluator and a switched-capacitor network is disclosed, which is in an analog and digital dual domain structure. The comparator offset evaluator receives digital data from an analog-to-digital conversion module, evaluates an offset of a comparator of the analog-to-digital conversion module based on the received digital data, and outputs an evaluated result. The switched-capacitor network processes the evaluated result to generate a control signal. The analog-to-digital conversion module adjusts the offset of the comparator according to the control signal.

Comparator offset calibration system and analog-to-digital converter with comparator offset calibration

A dynamic amplifier with a bypass design. An input pair of transistors receives a pair of differential inputs Vip and Vin and further provides first, second and third terminals. A load circuit provides a pair of differential outputs Vop and Von with the load circuit connected at a common mode terminal. In an amplification phase, a driver for amplification is coupled to the first terminal and the load circuit is coupled to the second and third terminals. A bypassing circuit is specifically provided. The bypassing circuit is coupled to the second and third terminals during a bypass period within the amplification phase.

Dynamic amplifier and chip using the same

A Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) including: a comparing module and a calibration circuit. The comparing module is arranged to generate a first comparison result by comparing an input voltage value of the SAR ADC with a first voltage value and a second result by comparing the input voltage value with a second voltage value; the calibration circuit coupled to the comparing module is for generating a determination result determining whether the input voltage value is in a range according to the first comparison result and the second comparison result, and enters a calibration mode according to the determination result.

Successive approximation register analog-to-digital converter applying calibration circuit, associated calibrating method, and associated electronic device

An interleaving successive approximation analog-to-digital converter (SAR ADC) with noise shaping having a first SAR block, a second SAR block, and a noise-shaping circuit is provided. The first and second SAR blocks take turns to sample an input voltage for successive approximation of the input voltage and observation of a digital representation of the input voltage. The noise-shaping circuit receives a first residue voltage from the first SAR block and receives a second residue voltage from the second SAR block alternately, and outputs a noise-shaping signal to be fed into the first SAR block and the second SAR block.

Interleaving successive approximation analog-to-digital converter with noise shaping

An ultrasonic scanning system includes a host device, an ultrasonic probe, and at least two electrodes. The ultrasonic probe is electrically connected to the host device for performing an ultrasonic scanning operation toward a detecting region to generate a scanning signal and to transmit the scanning signal to the host device. The at least two electrodes are disposed on the ultrasonic probe and are connected to the host device for detecting a physiological signal of the detecting region and transmitting the physiological signal to the host device.

Ultrasonic scanning system

An analog-to-digital converter (ADC) using an amplifier-based noise shaping circuit. The amplifier-based noise shaping circuit generates a noise shaping signal. A comparator of the ADC has a first input terminal coupled to an output terminal of a capacitive data acquisition converter that captures an analog input, a second input terminal receiving the noise shaping signal, and an output terminal for observation of the digital representation of the analog input. The amplifier-based noise shaping circuit uses an amplifier to amplify a residual voltage obtained from the capacitive data acquisition converter and provides a switched capacitor network between the amplifier and the comparator for sampling the amplified residual voltage and generating the noise shaping signal.

Analog-to-digital converter with noise shaping

A hybrid analog-to-digital converter (ADC) includes a plurality of analog-to-digital conversion circuits and a combining circuit. The analog-to-digital conversion circuits generate a plurality of partial digital outputs for a same analog input, respectively, wherein the analog-to-digital conversion circuits include a digital slope ADC used to perform signal quantization in a time domain. The combining circuit combines the partial digital outputs generated from the analog-to-digital conversion circuits to generate a final digital output of the analog input.

Hybrid analog-to-digital converter using digital slope analog-to-digital converter and related hybrid analog-to-digital conversion method thereof

A SAR ADC is provided. A DAC provides an intermediate analog signal according to an analog input signal, a most significant bit capacitance and a plurality of significant bit capacitances smaller than the most significant bit capacitance. A first switched capacitor array selectively provides the most significant bit capacitance or the significant bit capacitances according to a select signal. Sum of the significant bit capacitances is equal to the most significant bit capacitance. The second switched capacitor array provides the significant bit capacitances when the first switched capacitor array provides the most significant bit capacitance, and provides the most significant bit capacitance when the first switched capacitor array provides the significant bit capacitances. A comparator provides a comparison result according to the intermediate analog signal. A SAR logic provides an digital output signal according to the comparison result.

Successive approximation register analog to digital converters

A successive approximation register analog-to-digital converter (SAR ADC) for high-speed applications. The SAR ADC uses at least one set of capacitors. Each set of capacitors is formed by 2capacitor cells. The set of 2capacitor cells is allocated into p capacitors C(p&#x2212;1) to Cdecreasing in capacitance. C(p&#x2212;1)&#x3c;C(p&#x2212;2)+C(p&#x2212;3)+ . . . +C, and C(p&#x2212;1) includes (2&#x2212;2) capacitor cells.

Growing community of inventors

Xianxi, Taiwan

Chun-Cheng Liu