Taiwan Semiconductor Manufacturing Comp. Ltd.

Dell Products Inc.

Academia Sinica

Other

The Scripps Research Institute

Hewlett-packard Development Company, L.P.

Wistron Corporation

National Taiwan University

Compal Electronics, Inc.

National Taiwan Normal University

Dell & Products L.p.

Innomind Solution Company Limited

Chun-Cheng Lin

Chung-Shi Liu

Ming-Da Cheng

Chih-Wei Lin

Meng-Tse Chen

Kuei-Wei Huang

Wei-Hung Lin

Hsiu-Jen Lin

Yu-Peng Tsai

Wen-Hsiung Lu

Cheng-Ting Chen

Chen-Hua Douglas Yu

Ching-Hua Hsieh

Yu-LIn Chen

Hao-Yi Tsai

Chi-Huey Wong

Mao-Yen Chang

Tin-Hao Kuo

Chun-Hung Lin

Yu-Chia Lai

Chih-Hsuan Tai

Bor-Ping Jang

Kuo-Lung Pan

Yueh-Chun Tsai

Wei-Yu Chen

Yu-Feng Chen

Shui-Tein Chen

Hong-Sen Chen

Yow-Fu Tsai

Kay-Hooi Khoo

Yuan-Yuan Wang

Chen-Shien Chen

Mirng-Ji Lii

Yu-Chih Huang

Hui-Min Huang

Wei-Ting Lin

Chin-Liang Chen

Kuan-Lin Ho

Sheng-Yu Wu

Shih-Yen Lin

Yu-Chih Liu

Cheng-Chung Lin

Chih-Chiang Tsao

Hsaing-Pin Kuan

Kai-Chiang Wu

Han-Ping Pu

Hsuan-Ting Kuo

Brandon Joel Brocklesby

Yu-Wei Lin

Ai-Tee Ang

Yi-Da Tsai

Liang-Chun Ma

Chi-Feng Lee

Yu-Lin Chen

Chih Min Su

Chi-Chung Ho

Chia-Chun Chen

Jaulang Hwang

Yu-Ju Chen

Chun-Yen Lan

Li Liu

Tetsuya Kajimoto

Cheng-Tar Wu

Jen-Chun Hsueh

Chih-Chun Chiu

Francisco Moris-Varas

Hong-Wen Lee

Yi-Chun Wu

Shu-Hua Chen

Po Hsiang Liao

Chih-Hsiang Tang

Shy-Luen Chern

Hsin-Kai Liao

Po-Hung Chou

Yenlin Wang

Po-Chiao Lin

Chia-Tse Shu

Chiao-En Chen

Fan-Dan Jan

Hsiao-Ling Chiang

Hsing-Yuan Shen

Kuang-Jye Tuan

Ching-Shi Liu

Hsiang Jung Chin

Chun Chin Wen

A semiconductor package and a manufacturing method thereof are described. The semiconductor package includes a package having dies encapsulated by an encapsulant, a redistribution circuit structure, first and second modules and affixing blocks. The redistribution circuit structure is disposed on the package. The first and second modules are disposed on and respectively electrically connected to the redistribution circuit structure by first and second connectors disposed there-between. The first and second modules are adjacent to each other and disposed side by side on the redistribution circuit structure. The affixing blocks are disposed on the redistribution circuit structure and between the first and second modules and the redistribution circuit structure. The affixing blocks include first footing portions located below the first module, second footing portions located below the second module, and exposed portions exposed from the first and second modules. The affixing blocks join the first and second modules to the redistribution circuit structure.

Semiconductor package and manufacturing method of the same

A flexible orientation rack cabinet includes a top panel, a bottom panel, first and second edge panels, a first and second flexible mounting flanges. The top panel includes a first U-space adjustment portion. The bottom panel includes a second U-space adjustment portion. The first flexible mounting flange is in physical communication with the first edge panel and includes a third U-space adjustment portion. The second flexible mounting flange is in physical communication with the second edge panel and includes a fourth U-space adjustment portion. The flexible orientation rack cabinet is in a first orientation when multiple first server rails are attached to the first and second U-space adjustment portions.

Flexible rack cabinet design

A power supply unit includes a main portion and a dual direction cooling fan. The main portion includes a cooling fan slot. The dual direction cooling fan inserted within cooling fan slot of the main portion. The dual direction cooling fan includes first, second, third, and fourth panels. The first panel is positioned toward a middle line of the main portion and the second positioned toward an outside edge of the main portion when the dual direction cooling fan is inserted within the cooling fan slot. The third panel is positioned toward a top panel of the main portion when the dual direction cooling fan is in a reverse airflow orientation. The fourth panel is positioned toward the top panel of the main portion when the dual direction cooling fan is in a normal airflow orientation.

Power supply unit with consolidated different airflow direction fans

A method of fabricating a semiconductor structure includes the following steps. A semiconductor wafer is provided. A plurality of first surface mount components and a plurality of second surface mount components are bonded onto the semiconductor wafer, wherein a first portion of each of the second surface mount components is overhanging a periphery of the semiconductor wafer. A first barrier structure is formed in between the second surface mount components and the semiconductor wafer. An underfill structure is formed under a second portion of each of the second surface mount components, wherein the first barrier structure blocks the spreading of the underfill structure from the second portion to the first portion.

Method of fabricating semiconductor structure including a barrier structure in between a plurality of surface mount components and a wafer

An electrical connector assembly including a first connector and a second connector to be mated with each other is provided. The first connector includes a first body, and at least one first terminal and multiple second terminals disposed therein. The second terminals are symmetrically arranged at opposite sides of the first terminal. The second connector includes a second body, at least one third terminal movably disposed in the second body, multiple fourth terminals disposed in the second body and symmetrically arranged at opposite sides of the third terminal, and a driving module electrically connected to at least one of the fourth terminals and structurally connected to the third terminal. In the mating process of the first and second connector, the second terminals and the fourth terminals are electrically connected firstly, to trigger the driving module to move the third terminal to be structurally and electrically connected to the first terminal.

Electrical connector assembly

A semiconductor package including a circuit substrate, an interposer structure, a plurality of dies, and an insulating encapsulant is provided. The interposer structure is disposed on the circuit substrate. The plurality of dies is disposed on the interposer structure, wherein the plurality of dies is electrically connected to the circuit substrate through the interposer structure. The insulating encapsulant is disposed on the circuit substrate, wherein the insulating encapsulant surrounds the plurality of dies and the interposer structure and encapsulates at least the interposer structure, the insulating encapsulant has a groove that surrounds the interposer structure and the plurality of dies, and the interposer structure and the plurality of dies are confined to be located within the groove.

Semiconductor package and method of fabricating the same

A carrier assembly for mounting equipment into a carrier slot includes an electro-magnetic interference (EMI) shield and an EMI finger. The EMI shield protects the mounted equipment from EMI. The EMI shield is formed in a first plane of the carrier assembly. The EMI finger protrudes from the EMI shield and is coupled to the EMI shield. The EMI finger is formed in a second plane perpendicular to the first plane. The EMI finger operates, when the carrier assembly is installed into the carrier slot, to couple the EMI shield to the carrier slot. The EMI finger, when viewed from a first direction that is perpendicular to both the first plane and the second plane, is formed in a tear-drop shape.

Tear-drop shaped HDD carrier EMI finger

A semiconductor structure includes a semiconductor wafer, a first surface mount component, a second surface mount component and a first barrier structure. The first surface mount component is disposed on the semiconductor wafer, and electrically connected to the semiconductor wafer through a plurality of first electrical connectors. The second surface mount component is disposed on the semiconductor wafer, and electrically connected to the semiconductor wafer through a plurality of second electrical connectors, wherein an edge of the second surface mount component is overhanging a periphery of the semiconductor wafer. The first barrier structure is disposed on the semiconductor wafer in between the second electrical connectors and the edge of the second surface mount component, wherein a first surface of the first barrier structure is facing the second electrical connectors, and a second surface of the first barrier structure is facing away from the second electrical connectors.

Semiconductor structure including a semiconductor wafer and a surface mount component overhanging a periphery of the semiconductor wafer

Semiconductor structure including a first surface mount component and a second surface mount component and method of fabricating the semiconductor structure

Provided is a package structure including a composite wafer, a plurality of dies, an underfill, and a plurality of dam structures. The composite wafer has a first surface and a second surface opposite to each other. The composite wafer includes a plurality of seal rings dividing the composite wafer into a plurality of packages; and a plurality of through holes respectively disposed between the seal rings and penetrating through the first and second surfaces. The dies are respectively bonded onto the packages at the first surface by a plurality of connectors. The underfill laterally encapsulates the connectors. The dam structures are disposed on the first surface of the composite wafer to separate the underfill from the through holes.

Package structure and method of forming the same

Systems and methods for a flexible Power Supply Unit (PSU) bay are described. In some embodiments, a chassis may include a surface and a PSU adaptor disposed on the surface, the PSU adaptor comprising a tab having a stopper coupled thereto, where the stopper is configured to: (a) resist movement, bending, or deformation of a board perpendicularly disposed with respect to the surface upon insertion of a first PSU into a PSU cage, and (b) move downward upon insertion of a second PSU into the PSU cage.

Flexible power supply unit (PSU) bay

A system and method for packaging semiconductor dies is provided. An embodiment comprises a first package with a first contact and a second contact. A post-contact material is formed on the first contact in order to adjust the height of a joint between the contact pad a conductive bump. In another embodiment a conductive pillar is utilized to control the height of the joint between the contact pad and external connections.

Semiconductor packaging structure and method

A semiconductor structure and a manufacturing method thereof are provided. A semiconductor structure includes a first semiconductor die, an insulating encapsulation laterally encapsulating the first semiconductor die, an electromagnetic shielding structure enclosing the first semiconductor die and a first portion of the insulating encapsulation, and a redistribution structure. The electromagnetic shielding structure includes a first conductive layer and a dielectric frame laterally covering the first conductive layer. The first conductive layer surrounds the first portion of the insulating encapsulation and extends to cover a first side of the first semiconductor die. The dielectric frame includes a first surface substantially leveled with the first conductive layer. The redistribution structure is disposed on a second side of the first semiconductor die opposing to the first side, and the redistribution structure is electrically coupled to the first semiconductor die and the first conductive layer of the electromagnetic shielding structure.

Semiconductor structure and manufacturing method thereof

Packaging methods for semiconductor devices are disclosed. A method of packaging a semiconductor device includes providing a workpiece including a plurality of packaging substrates. A portion of the workpiece is removed between the plurality of packaging substrates. A die is attached to each of the plurality of packaging substrates.

Packaging methods for semiconductor devices comprising forming trenches in separation regions between adjacent packaging substrates

Growing community of inventors

Taipei, Taiwan

Chun-Cheng Lin