Taiwan Semiconductor Manufacturing Comp. Ltd.

Chun-Cheng Ku

Yi-Lin Chuang

Wei-Pin Changchien

Chin-Her Chien

Yun-Han Lee

Jack Liu

Chin-Chou Liu

Shao-Yu Wang

An integrated circuit (IC) semiconductor device has a high oxide definition (OD) density region, a low OD density region adjacent to the high OD density region, and dummy cells in the high OD density region and the low OD density region to smooth a density gradient between the high OD density region and the low OD density region.

Oxide definition (OD) gradient reduced semiconductor device

A method of reducing an oxide definition (OD) density gradient in an integrated circuit (IC) semiconductor device having a placed layout and a set of design rule checking (DRC) rules associated with the placed layout. The method includes computing OD density in insertion regions from OD density information corresponding to the placed layout to identify an OD density gradient. The method further includes selecting and adding dummy cells to at least one insertion region to reduce the OD density gradient.

Oxide definition (OD) gradient reduced semiconductor device and method of making

A semiconductor device is disclosed that includes a clock signal distribution network and a logic circuitry. The clock signal distribution network is configured to receive a first power. The logic circuitry is configured to receive a second power independent from the first power.

Power distribution in semiconductor device

Among other things, one or more systems and techniques for defining a group bounding box for related cells of an integrated circuit, and generating a new layout for the integrated circuit comprising the group bounding box are provided herein. That is, one or more group bounding boxes are defined based upon positional values of related cells. Such group bounding boxes are placed within the new layout based upon a placement technique, such as an objective function that takes into account wire length, timing, and cell density, for example. The one or more group bounding boxes are sized or reshaped to reduce cell overlap within the new layout. In this way, the new layout comprises related cells, bound by one or more group bounding boxes, that are placed within the new layout according to a configuration that mitigates wire length and timing delay of the integrated circuit.

Growing community of inventors

Zhubei, Taiwan

Chun-Cheng Ku