Synopsys, Inc.

Chun-Cheng Chi

Shih-Pin Hung

Tung-Chieh Chen

Chien-Hung Lu

Sanjiv Mathur

Bing Chen

Sivakumar Arulanantham

Srinivasan Krishnamurthy

Yi-Ting Chung

Kaichih Chi

Prakasha Karkada Holla

Kuan-Yu Liao

Anusha Reddy Sindhwala

Ashima Sahil Dabare

Embodiments provide for building a global clock tree. In embodiments, an example method includes inserting clock drivers at symmetric locations in one or more hierarchy levels of a plurality of hierarchy levels of an integrated circuit (IC) design. The example method further includes generating one or more routes by routing one or more nets within or across the one or more hierarchy levels of the plurality of hierarchy levels. The example method further includes matching symmetric routes of the one or more routes at each of the one or more hierarchy levels irrespective of a number of physical hierarchies each associated net spans. The example method further includes placing one or more ports at one or more signal entry points where routes of the one or more routes cross physical hierarchy blocks.

Automated balanced global clock tree synthesis in multi level physical hierarchy

Techniques and systems for automatic net grouping and routing are described. Some embodiments can determine a set of net groups by automatically grouping nets that have (1) a same pin count, (2) a pin direction type that is in a predefined set of pin direction types, and (3) a pin order type that is in a predefined set of pin order types. Next, the embodiments can generate routing guidance by performing trunk planning for each net group. The embodiments can then perform detailed routing for each net in each net group by using the routing guidance.

Automatic net grouping and routing

A computer implemented method of routing a net of an electronic circuit is disclosed. The net connects a plurality of pins of the electronic circuit. The method includes selecting, using one or more computer systems, first and second main spine routing tracks for respective first and second groups of pins of the net. The method also includes generating, using one or more computer systems, a first main spine wire on the selected first main spine routing track and a second main spine wire on the selected second main spine routing track. A router configured to perform the method is also disclosed.

Spine routing with multiple main spines

Growing community of inventors

Mountain View, CA, United States of America

Chun-Cheng Chi