Powerchip Technology Corporation

Taiwan Semiconductor Manufacturing Comp. Ltd.

Powerchip Semiconductor Manufacturing Corporation

Silicon Integrated Systems Corporation

Global Unichip Corporation

National Applied Research Laboratories

Chun-Cheng Chen

Chan-Ching Lin

Chen-Hao Huang

Tzung-Bin Huang

Chih-Yuan Chen

Ching-Hua Chen

Hui-Huang Chen

Hung-Chih Lin

Chun-Lin Lu

Mill-Jer Wang

Shou-Zen Chang

Hao Chen

Chun-Yu Lin

Ching-Nen Peng

Wen-Tai Wang

Chi-Hung Huang

Tsun-Hsu Chang

Chong-Jen Huang

Cheng-Fang Ho

Wei-Yao Hsu

Po-Jui Chen

Ming-Fu Chen

Yi-Hao Lin

Hann-Ping Hwang

Wei-Jei Peng

Zong-Ru Yu

Jung-Hsin Wang

Hua-Lin Chen

Ching-Ching Tsai

Ting-Jyun He

Tai-Liang Hsiung

Sheng-Fu Yang

A memory device is provided. The memory device includes at least one memory chip and a logic chip. Each of the at least one memory chip includes a memory array, a plurality of bit lines, and a plurality of data paths. The data paths respectively correspond to the bit lines. The number of the data paths is equal to or less than the number of the bit lines. A plurality of data transmission ports of the logic chip are electrically connected to the data paths of the at least one memory chip in a one-to-one manner. The number of the data transmission ports is equal to a sum of the data paths of the at least one memory chip.

Memory device with high data bandwidth

A circuit structure for testing through silicon vias (TSVs) in a 3D IC, including a TSV area with multiple TSVs formed therein, and a switch circuit with multiple column lines and row lines forming an addressable test array, wherein two ends of each TSV are connected respectively with a column line and a row line. The switch circuit applies test voltage signals through one of the row lines to the TSVs in the same row and receives current signals flowing through the TSVs in the row from the columns lines, or the switch circuit applies test voltage signals through one of the column lines to the TSVs in the same column and receives current signals flowing through the TSVs in the column from the row lines.

Circuit structure for testing through silicon vias in three-dimensional integrated circuit

A semiconductor structure corresponds to a first diode and a second diode connected in series. A first well region is on a first deep well region. Two second well regions are at two sides of the first well region respectively. A first doping region and a second doping region are on the first well region. A first isolation region is between the first doping region and the second doping region. A third well region is on a second deep well region. Two fourth well regions are at two sides of the third well region respectively. A third doping region and a fourth doping region are on the third well region. A second isolation region is between the third doping region and the fourth doping region. The second doping region and third doping region are connected. The second deep well region is separated from the first deep well region.

Semiconductor structure and electrostatic discharge protection circuit

The present disclosure illustrates a non-contact measurement device for a radius of curvature and a thickness of a lens and a measurement method thereof. The non-contact measurement device utilizes a non-contact probe to integrate a motor, an optical scale and an electronic control module, so as to achieve measurement for the radius of curvature and the thickness of the lens. The present disclosure adopts astigmatism to achieve fast and precise focusing. To overcome the spherical aberration problem, thickness measurement can be implemented by the non-contact measurement device through a formula calculation and utilization of a correction plate, wherein single one probe is used for the measurement herein. For the thicker lens, the non-contact measurement device can be extended to use dual probes, so as to detect the top and bottom sides of the lens.

Non-contact measurement device for radius of curvature and thickness of lens and measurement method thereof

This invention provides a memory structure and an operation method thereof. The memory structure includes a triode for alternating current (TRIAC) and a memory cell. The memory cell is electrically connected to the TRIAC.

Memory structrue and operation method thereof

A method includes testing a first device and a second device identical to each other and comprising integrated circuits. The testing of the first device is performed according to a first test sequence of the first device, wherein the first test sequence includes a plurality of ordered test items, and wherein the first test sequence includes a test item. A test priority of the test item is calculated based on a frequency of fails of the test item in the testing of a plurality of devices having an identical structure as the first device. The first test sequence is then adjusted to generate a second test sequence in response to the test priority of the test item, wherein the second test sequence is different from the first test sequence. The second device is tested according to the second test sequence.

Adaptive test sequence for testing integrated circuits

A method of fabricating a resistive random access memory (RRAM) device is disclosed. A plurality of word lines extending along a first direction are formed on a substrate with a recess between the word lines. A spacer-type resistance layer and a top electrode layer are formed on a sidewall of each of the word lines. A photoresist stripe pattern extending along a second direction is then formed on the substrate. The first direction is perpendicular to the second direction. An etching process is performed to remove the top electrode layer and the spacer-type resistance layer not covered by the photoresist stripe pattern to form a plurality of top electrodes. A diode is formed on each of the top electrodes.

Method for fabricating resistive random access memory

A resistive random access memory (RRAM) unit includes at least one bit line extending along a first direction, at least one word line disposed on a substrate and extending along a second direction so as to intersect the bit line, a hard mask layer on the word line to isolate the word line from the bit line, a first memory cell on a sidewall of the word line, and a second memory cell on the other sidewall of the word line.

Resistive random access memory and fabrication method thereof

A vertical capacitor-less DRAM cell is described, including: a source layer having a first conductivity type, a storage layer disposed on the source layer and having a second conductivity type, an active layer disposed on the storage layer and having the first conductivity type, a drain layer disposed on the active layer and having the second conductivity type, an address gate disposed beside the active layer and separated from the same by a first gate dielectric layer, and a storage gate disposed beside the storage layer and separated from the same by a second gate dielectric layer. The DRAM cell can be written by turning on the MOSFET formed by the storage layer, the active layer, the drain layer, the first gate dielectric layer and the address gate to inject carriers into the storage layer from the active layer.

Vertical capacitor-less DRAM cell, DRAM array and operation of the same

A dynamic random access memory cell having vertical channel transistor includes a semiconductor pillar, a drain layer, an assisted gate, a control gate, a source layer, and a capacitor. The vertical channel transistor has an active region formed by the semiconductor pillar. The drain layer is formed at the bottom of the semiconductor pillar. The assisted gate is formed beside the drain layer, and separated from the drain layer by a first gate dielectric layer. The control gate is formed beside the semiconductor pillar, and separated from the active region by a second gate dielectric layer. The source layer is formed at the top of the semiconductor pillar. The capacitor is formed to electrical connect to the source layer.

Dynamic random access memory cell and array having vertical channel transistor

Voltage fluctuations, especially due to a resonant effect of a power distribution system, result in serious timing skews in a high-speed digital system. Adding extra resistive loadings for coupling out the noise into external terminations will reduce a quality factor of the power distribution system, which will effectively minimize the noise accumulation. The external coupled resistive terminators are preferably formed on positions of a microstrip resonator where relatively high noise fluctuations occur. Each of the external coupled resistive terminators may be formed of a resistor, a transmission line with a resistor at one end, a lossy transmission line with an open circuit at one end, or a quarter-wavelength lossy transmission line. Simulation results indicate that the maximum voltage fluctuations are suppressed from 750 mV to 150 mV at a resonant frequency and about 50% for an overall range of the operating frequencies.

Method of reducing switching noise in a power distribution system by external coupled resistive terminators

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Hsinchu, Taiwan

Chun-Cheng Chen