International Business Machines Corporation

Globalfoundries Inc.

Stmicroelectronics Gmbh

Renesas Electronics Corporation

Adeia Semiconductor Bonding Technologies Inc.

Kabushiki Kaisha Toshiba

Elpis Technologies Inc.

Chun-chen Yeh

Tenko Yamashita

Veeraraghavan S Basker

Ruilong Xie

Zuoguang Liu

Qing Liu

Kangguo Cheng

Xiuyu Cai

Chiahsun Tseng

Yunpeng Yin

Dechao Guo

Hong He

Effendi Leobandung

Shogo Mochizuki

Ming Cai

Sanjay C Mehta

Kejia Wang

Hui Zang

Junli Wang

Ali Khakifirooz

Juntao Li

Liyang Song

Xin Miao

Oleg Gluschenkov

Chung-Hsun Lin

Hiroaki Niimi

Wilfried Haensch

Bruce Bennett Doris

David V Horak

Theodorus E Standaert

Nicolas J Loubet

Hemanth Jagannathan

Balasubramanian Pranatharthiharan

Pranita Kulkarni

Huiming Bu

Stefan Schmitz

Andres Bryant

Miaomiao Wang

Andreas Scholze

Terence B Hook

Soon-Cheon Seo

Praneet Adusumilli

Hsueh-Chung Chen

Andrew Mark Greene

Pranita Kerber

Chia-Yu Chen

Paul Michael Solomon

Chi-Chun Liu

Daniel Chanemougame

Muthumanickam Sankarapandian

Cheng Chi

William James Taylor, Jr

Akira Hokazono

Hiroshi Itokawa

Derrick Liu

Yulong Li

Jin Haeng Cho

Lei L Zhuang

Krishna Iyengar

Alexander Reznicek

Jeffrey Bowman Johnson

Zhen Zhang

Shreesh Narasimha

Su Chen Fan

Unoh Kwon

William K Henson

Hyun-Jin Cho

Raghavasimhan Sreenivasan

Gen Tsutsui

Yanfeng Wang

Yue Liang

Maryjane Brodsky

Ailian Zhao

Yunpeg Yin

Tanko Yamashita

Techniques for forming a metastable phosphorous P-doped silicon Si source drain contacts are provided. In one aspect, a method for forming n-type source and drain contacts includes the steps of: forming a transistor on a substrate; depositing a dielectric over the transistor; forming contact trenches in the dielectric that extend down to source and drain regions of the transistor; forming an epitaxial material in the contact trenches on the source and drain regions; implanting P into the epitaxial material to form an amorphous P-doped layer; and annealing the amorphous P-doped layer under conditions sufficient to form a crystalline P-doped layer having a homogenous phosphorous concentration that is greater than about 1.5&#xd7;10atoms per cubic centimeter (at./cm). Transistor devices are also provided utilizing the present P-doped Si source and drain contacts.

Low resistance source drain contact formation with trench metastable alloys and laser annealing

A method of forming a semiconductor device that includes forming a fin structure from a bulk semiconductor substrate and forming an isolation region contacting a lower portion of a sidewall of the fin structure, wherein an upper portion of the sidewall of the fin structure is exposed. A sacrificial spacer is formed on the upper portion of the sidewall of the fin structure. The isolation regions are recessed to provide an exposed section of the sidewall of the fin structure. A doped semiconductor material is formed on the exposed section of the lower portion of the sidewall of the fin structure. Dopant is diffused from the doped semiconductor material to a base portion of the fin structure.

Punch through stopper in bulk finFET device

A method of forming the fin structure that includes forming a replacement gate structure on a channel region of the at least one replacement fin structure; and forming an encapsulating dielectric encapsulating the replacement fin structure leaving a portion of the replacement gate structure exposed. The exposed portion of the replacement gate structure is etched to provide an opening through the encapsulating dielectric to the replacement fin structure. The replacement fin structure is etched selectively to the dielectric to provide a fin opening having a geometry dictated by the encapsulating dielectric. Functional fin structures of a second semiconductor material is epitaxially grown on the growth surface of the substrate substantially filling the fin opening.

Aspect ratio trapping in channel last process

A method of forming a punch through stop region in a fin structure is disclosed. The method may include forming a doped glass layer on a fin structure and forming a masking layer on the doped glass layer. The method may further include removing a portion of the masking layer from an active portion of the fin structure, and removing an exposed portion the doped glass layer that is present on the active portion of the fin structure. A remaining portion of the doped glass layer is present on the isolation portion of the fin structure. Dopant from the doped glass layer may then be diffused into the isolation portion of the fin structure to form the punch through stop region between the active portion of the fin structure and a supporting substrate.

High thermal budget compatible punch through stop integration using doped glass

A semiconductor device that includes at least one fin structure and a gate structure present on a channel portion of the fin structure. An epitaxial semiconductor material is present on at least one of a source region portion and a drain region portion on the fin structure. The epitaxial semiconductor material includes a first portion having a substantially conformal thickness on a lower portion of the fin structure sidewall and a second portion having a substantially diamond shape that is present on an upper surface of the source portion and drain portion of the fin structure. A spacer present on first portion of the epitaxial semiconductor material.

Composite spacer enabling uniform doping in recessed fin devices

A method for fabricating a semiconductor device includes depositing a sacrificial liner in self-aligned contact openings in first and second regions. The openings are filled with a sacrificial material. The second region is blocked with a first mask to remove the sacrificial material from the first region. The first mask is removed from the second region, and the sacrificial liner is removed from the first region. A first liner is formed in the openings of the first region, and first contacts are formed in the first region on the first liner. The first region is blocked with a second mask to remove the sacrificial material from the second region. The second mask is removed from the first region, and the sacrificial liner is removed from the second region. A second liner is formed in the openings of the second region, and second contacts are formed in the second region.

Dual silicide liner flow for enabling low contact resistance

A substrate structure having a set of nanosheet layers and a set of sacrificial layers stacked upon a substrate is received and a dummy gate is formed upon the nanosheet layers and the sacrificial layers. A portion of a subset of the set of sacrificial layers and a subset of the set of nanosheet layers is etched. A portion of a subset of the subset of sacrificial layers is etched to create divots within the sacrificial layers. A divot fill layer is deposited. The divot fill layer is etched to form an inner spacer between the nanosheet layers. A source/drain region is formed adjacent to the nanosheet layers and the divots. A remaining portion of the subset of the sacrificial layers is removed. The subset of the nanosheet layers is etched to a desired channel thickness producing faceted surfaces between the subset of nanosheet layers and the inner spacer.

Nanosheet transistor with optimized junction and cladding detectivity control

A semiconductor material layer is deposited on a p-type source/drain region of a p-type transistor device and an n-type source/drain region of an n-type transistor device. The p-type device transistor device and the n-type transistor device are formed on a substrate of a semiconductor device. The semiconductor device includes a trench formed through an inter-level dielectric layer. The inter-level dielectric layer is formed over the n-type transistor device and the p-type transistor device. The trench exposes the p-type source/drain region of the p-type transistor device and the n-type source/drain region of the n-type transistor device. An element is implanted in the semiconductor material layer to form an amorphous layer on p-type source drain region and the n-type source/drain region. The amorphous layer is annealed to form a first metastable alloy layer upon the p-type source/drain region and a second metastable alloy layer upon the n-type source/drain region.

Contact formation through low-tempearature epitaxial deposition in semiconductor devices

A method of forming a gate structure, including forming one or more vertical fins on a substrate; forming a bottom spacer on the substrate surface adjacent to the one or more vertical fins; forming a gate structure on at least a portion of the sidewalls of the one or more vertical fins; forming a gauge layer on at least a portion of the bottom spacer, wherein the gauge layer covers at least a portion of the gate structure on the sidewalls of the one or more vertical fins; and removing a portion of the gauge layer on the bottom spacer.

Fabrication of vertical field effect transistor structure with controlled gate length

A method of forming a fin field effect transistor (finFET), including forming a temporary gate structure having a sacrificial gate layer and a dummy gate layer on the sacrificial gate layer, forming a gate spacer layer on each sidewall of the temporary gate structure, forming a source/drain spacer layer on the outward-facing sidewall of each gate spacer layer, removing the dummy gate layer to expose the sacrificial gate layer, removing the sacrificial gate layer to form a plurality of recessed cavities, and forming a gate structure, where the gate structure occupies at least a portion of the plurality of recessed cavities.

Fin field effect transistor fabrication and devices having inverted T-shaped gate

A large area electrical contact for use in integrated circuits features a non-planar, sloped bottom profile. The sloped bottom profile provides a larger electrical contact area, thus reducing the contact resistance, while maintaining a small contact footprint. The sloped bottom profile can be formed by recessing an underlying layer, wherein the bottom profile can be crafted to have a V-shape, U-shape, crescent shape, or other profile shape that includes at least a substantially sloped portion in the vertical direction. In one embodiment, the underlying layer is an epitaxial fin of a FinFET. A method of fabricating the low-resistance electrical contact employs a thin etch stop liner for use as a hard mask. The etch stop liner, e.g., HfO, prevents erosion of an adjacent gate structure during the formation of the contact.

Large area contacts for small transistors

Contact formation through low-temperature epitaxial deposition in semiconductor devices

Techniques for VFET top source and drain epitaxy are provided. In one aspect, a method of forming a VFET includes: patterning a fin to form a bottom source/drain region and a fin channel of the VFET; forming bottom spacers on the bottom source/drain region; depositing a high-&#x3ba; gate dielectric onto the bottom spacers and along sidewalls of the fin channel; forming gates over the bottom spacers; forming top spacers on the gates; partially recessing the fin channel to create a trench between the top spacers; forming a nitride liner along sidewalls of the trench; fully recessing the fin channel through the trench such that side portions of the fin channel remain intact; and forming a doped epitaxial top source and drain region over the fin channel. Methods not requiring a nitride liner and VFET formed using the present techniques are also provided.

Techniques for VFET top source/drain epitaxy

Growing community of inventors

Clifton Park, NY, United States of America

Chun-chen Yeh