Taiwan Semiconductor Manufacturing Comp. Ltd.

Industrial Technology Research Institute

Pixart Imaging Incorporated

Chien Hwa Coating Technology, Inc.

Chun-Chen Chen

Sheng-Hsiung Chen

Po-Hsiang Huang

Shao-Huan Wang

Lee-Chung Lu

Fong-Yuan Chang

Chung-Te Lin

Fong-yuan Chang

Kuo-Nan Yang

Wen-Hao Chen

Chin-Chou Liu

Hung-Chih Ou

Li-Chun Tien

Chung-Hsing Wang

Ting-Wei Chiang

Yi-Kan Cheng

Jerry Chang Jui Kao

Ting Yu Chen

Yen-Pin Chen

Tzu-Hen Lin

Tai-Yu Cheng

Jung-Chan Yang

Jerry Chang-Jui Kao

XinYong Wang

Sheng-hsiung Chen

Yen-Min Chang

Jyun-Hao Chang

Meng-Xiang Lee

Yi-Wei Lin

Chih-Hui Alston Liu

Shao-huan Wang

Ren-Zheng Liao

Hui-Zhong Zhuang

Hsin-Chia Chen

Juin-Ming Lu

Teng-Chun Wu

Chung-hsing Wang

Chih-Tsun Huang

Jung-chan Yang

Yao-Hua Chen

Shu-Yu Chen

Jing-Jia Liou

Chun-Hung Lai

Meng-Hsueh Wang

Ming-Huei Tsai

Yu-Yi Cheng

Ming-Jia Li

Kou-Cheng Yeh

A logic cell structure includes a first portion, a second portion and a third portion. The first portion, arranged to be a first layout of a first semiconductor element, is placed in a first cell row of a substrate area extending in a first direction. The second portion, arranged to be a second layout of a second semiconductor element, is placed in a second cell row of the substrate area. The third portion is arranged to be a third layout of an interconnecting path used for coupling the first semiconductor element and the second semiconductor element. The first, second and third portions are bounded by a bounding box with a height in a second direction and a width in the first direction. Respective centers of the first portion and the second portion are arranged in a third direction different from each of the first direction and the second direction.

Logic cell structure and integrated circuit with the logic cell structure

An integrated circuit device includes a device layer having devices spaced in accordance with a predetermined device pitch, a first metal interconnection layer disposed above the device layer and coupled to the device layer, and a second metal interconnection layer disposed above the first metal interconnection layer and coupled to the first metal interconnection layer through a first via layer. The second metal interconnection layer has metal lines spaced in accordance with a predetermined metal line pitch, and a ratio of the predetermined metal line pitch to predetermined device pitch is less than 1.

Integrated circuit device with improved layout

An integrated circuit layout is provided. The integrated circuit layout includes one or more first cell rows partially extending across a space arranged for an integrated circuit layout along a first direction. Each of the one or more first cell rows has a first height along a second direction perpendicular to the first direction. The integrated circuit layout includes one or more third cell rows partially extending across the space along the first direction. Each of the one or more third cell rows has a second height along the second direction, the second height different from the first height.

Systems and methods for integrated circuit layout

An integrated circuit includes a cell that is between a substrate and a supply conductive line and that includes a source region, a contact conductive line, a power conductive line, and a power via. The contact conductive line extends from the source region. The power conductive line is coupled to the contact conductive line. The power via interconnects the supply conductive line and the power conductive line.

Integrated circuit having a high cell density

The present disclosure describes an example method for routing a standard cell with multiple pins. The method can include modifying a dimension of a pin of the standard cell, where the pin is spaced at an increased distance from a boundary of the standard cell than an original position of the pin. The method also includes routing an interconnect from the pin to a via placed on a pin track located between the pin and the boundary and inserting a keep out area between the interconnect and a pin from an adjacent standard cell. The method further includes verifying that the keep out area separates the interconnect from the pin from the adjacent standard cell by at least a predetermined distance.

Pin modification for standard cells

A system includes a non-transitory computer readable medium configured to store instructions thereon. The system further includes a processor connected to the non-transitory computer readable medium. The processor is configured to execute the instruction for comparing a size of a via pillar structure of a first layout pattern of a plurality of layout patterns with a size of a via pillar structure of a second layout pattern of the plurality of layout patterns, wherein each of the plurality of layout patterns meets an electromigration (EM) rule. The processor is further configured to execute the instructions for replacing, in a layout design, the first layout pattern with the second layout pattern in response to the size of the via pillar structure of the second layout pattern being less than the size of the via pillar structure of the first layout pattern.

System for designing semiconductor device

Standard cell libraries include one or more standard cells and one or more corresponding standard cell variations. The one or more standard cell variations are different from their one or more standard cells in terms of geometric shapes, locations of the geometric shapes, and/or interconnections between the geometric shapes. The exemplary systems and methods described herein selectively choose from among the one or more standard cells and/or the one or more standard cell variations to form an electronic architectural design for an electronic device. In some situations, some of the one or more standard cells are unable to satisfy one or more electronic design constraints imposed by a semiconductor foundry and/or semiconductor technology node when placed onto the electronic device design real estate. In these situations, the one or more standard cell variations corresponding to these standard cells are placed onto the electronic device design real estate.

Standard cells and variations thereof within a standard cell library

A DNN hardware accelerator and an operation method of the DNN hardware accelerator are provided. The DNN hardware accelerator includes: a network distributor for receiving an input data and distributing respective bandwidth of a plurality of data types of a target data amount based on a plurality of bandwidth ratios of the target data amount; and a processing element array coupled to the network distributor, for communicating data of the data types of the target data amount between the network distributor based on the distributed bandwidth of the data types.

Deep neural networks (DNN) hardware accelerator and operation method thereof

A method including selecting a plurality of layout patterns, wherein each of the layout patterns comprises a corresponding via pillar structure that satisfies an electromigration (EM) rule, wherein each of the via pillar structures comprises metal layers and at least one via coupled to the metal layers. The method further includes selecting a layout pattern from the plurality of layout patterns having a smallest physical size. The method further includes performing a placement and routing process by using the selected layout pattern.

Method of designing semiconductor device

Growing community of inventors

Hsinchu County, Taiwan

Chun-Chen Chen