Macronix International Co., Ltd.

Chun-Chang Lu

Wen-Jer Tsai

Wei-Liang Lin

Yao-Wen Chang

Guan-Wei Wu

Chih-Chieh Cheng

You-Liang Chou

Cheng-Hsien Cheng

Shaw-Hung Ku

A memory device and a reading method thereof are provided. A second word line and a third word line are adjacent to a first word line. The reading method includes the following steps. A read procedure is executed to read a plurality of memory cells of the first word line. When a read error occurs, a re-read procedure is executed for some of the memory cells belonging to a state marginal group. The read procedure includes: applying a read voltage to the first word line; applying a first pass voltage to the second word line and the third word line. The re-read procedure includes: applying the read voltage to the first word line; applying a second pass voltage and a third pass voltage different from the first pass voltage to the second word line and the third word line respectively.

Memory device and reading method thereof

A memory device and a reading method thereof are provided. The memory device at least includes a first word line, a second word line and a third word line. The reading method includes the following steps. A read procedure is executed to read a plurality of memory cells connected to the first word line. A recognition procedure is executed in response to at least one memory cell has an error. A re-read procedure is executed on the memory cell. The recognition procedure includes: applying a pass voltage to the first word line; applying a recognition voltage to at least one of the second word line and the third word line. The re-read procedure including: applying a second read voltage to the first word line; and applying a second pass voltage to the second word line and a third pass voltage to the third word line.

An operation method for a memory device is provided. The operation method includes: increasing a dummy word line voltage to a first dummy word line voltage during a pre-turn on period; increasing the dummy word line voltage from the first dummy word line voltage to a second dummy word line voltage during a read period; and lowering the dummy word line voltage after the read period is finished. Wherein the first dummy word line voltage is lower than the second dummy word line voltage.

Operation method for a memory device

A memory device and a method for operating selective erase scheme are provided. In an erase operation, a switch voltage is applied to at least one of a string select line or a ground select line of a selected sub-block of a selected block, a gate control voltage is applied to selected word lines of the selected sub-block, and an erase voltage is applied to bit lines and a common source line of the selected sub-block. The switch voltage is smaller than the erase voltage. The gate control voltage is smaller than the switch voltage and the erase voltage.

Memory device and method for operating selective erase scheme

An operation method for a memory device is provided. The operation method includes: increasing a dummy word line voltage to a first dummy word line voltage during a pre-tum on period; increasing the dummy word line voltage from the first dummy word line voltage to a second dummy word line voltage during a read period; and lowering the dummy word line voltage after the read period is finished. Wherein the first dummy word line voltage is lower than the second dummy word line voltage.

Provided are a memory device and an operation method thereof. The memory device includes a plurality of word lines. The operation method comprising: performing a pre-fill operation on the word lines, in a first loop, applying a selected word line voltage on a first selected word line group and applying an unselected word line voltage on a first unselected word line group, and in a second loop, applying the selected word line voltage on a second selected word line group and applying the unselected word line voltage on a second unselected word line group, the first selected word line group being different from the second selected word line group, and the first unselected word line group being different from the second unselected word line group; performing an erase operation on the word lines; and performing a programming operation on the word lines.

Memory device and operation method thereof

A memory device includes a conductive strip stack structure having conductive strips and insulating layers stacked in a staggered manner and a channel opening passing through the conductive strips and the insulating layer; a memory layer disposed in the channel opening and overlying the conductive strips; a channel layer overlying the memory layer; a semiconductor pad extending upwards from a bottom of the channel opening beyond an upper surface of a bottom conductive strip, in contact with the channel layer, and electrically isolated from the conductive strips; wherein the channel layer includes a first portion having a first doping concentration and a second portion having a second doping concentration disposed on the first portion.

Memory device and method for fabricating the same

A memory device is provided. The memory device includes a plurality of memory cell blocks and a source voltage generator. Each of the memory cell blocks has at least one memory cell. The source voltage generator is coupled to the plurality of memory cell blocks and configured to cause a source voltage of the memory cell block to be a first voltage according to that a memory cell in each of the memory cell blocks is in a selected state and cause a source voltage of the memory cell block to be a second voltage according to that all memory cells in each of the memory cell blocks are in an unselected state, wherein an absolute value of the first voltage is less than an absolute value of the second voltage. In addition, an operating method of the memory device is also provided.

Memory device and operating method thereof that reduce off current to reduce errors in reading and writing data which have plurality of memory cell blocks and a source voltage generator

A programming operation for high density memory, like 3D NAND flash memory, modifies the waveforms applied during program operations to mitigate unwanted disturbance of memory cells not selected for programming during the operation. Generally, the method provides for applying a bias arrangement during an interval of time between program verify pass voltages and program pass voltages in a program sequence that can include a soft ramp down, and pre-turn-on voltages designed to reduce variations in the potential distribution on floating channels of unselected NAND strings during a program operation.

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Yunlin County, Taiwan

Chun-Chang Lu