Taiwan Semiconductor Manufacturing Comp. Ltd.

Epistar Corporation

TSMC Nanjing Company, Limited

Chun-Chang Chen

Feng-Jia Shiu

Wang-Pen Mo

Chihy-Yuan Cheng

Ching-Sen Kuo

Shun-Shing Yang

Hung-Chang Hsieh

Chih-Chien Wang

Sz-Fan Chen

Wei-Lin Chang

Hsu-Cheng Lin

Chun-Chang Wu

Ying-Lang Wang

Min-Hsun Hsieh

Shih-Chi Fu

Yu-Ku Lin

Chou-Chih Yin

Pei-Shan Fang

Ching-Yi Chiu

Chuan-Ling Wu

Kei-Wei Chen

Shih-Chieh Chang

Tsun-Kai Ko

Chun-Wei Chang

Yi-Ming Chen

Chen Ou

De-Shan Kuo

Jung-Chih Tsao

Hsin-Ying Wang

Wen-Hung Chuang

Shih-Ho Lin

Jen-Shui Wang

Chia-Fen Tsai

Chia-Chen Tsai

Chen-Ke Hsu

Hong-Da Lin

Min Han Hsu

Chyi-Yang Sheu

Win-Jim Su

Mei-Ling Tsai

Yi-Lang Wang

Yi Lung Liu

Huai-Tei Yang

Chien-Hung Lin

Ting-Chun Wang

Hsi-Kuei Cheng

Lin-June Wu

Hung Chang Hsieh

Hung-Ju Chien

Shih-Tzung Chang

Tao Cheng

Chun-Ching Tsan

Liang-Sheng Chi

Chin-Te Huang

Tong-Hua Kuan

Liang Sheng Chi

Chien-hung Lin

Jiun-Pyng You

Cheng-Hsien Chuang

Ting-Chu Wang

Aaron Cheng

Wen-Hsin Huang

Ming-Jei Lee

Embodiments are directed to a method for minimizing electrostatic charges in a semiconductor substrate. The method includes depositing photoresist on a semiconductor substrate to form a photoresist layer on the semiconductor substrate. The photoresist layer is exposed to radiation. The photoresist layer is developed using a developer solution. The semiconductor substrate is cleaned with a first cleaning liquid to wash the developer solution from the photoresist layer. A tetramethylammonium hydroxide (TMAH) solution is applied to the semiconductor substrate to reduce charges accumulated in the semiconductor substrate.

Method for reducing charging of semiconductor wafers

A method includes depositing a metallic hardmask over a dielectric layer. The method further includes etching a metallic hardmask opening in the metallic hardmask to expose a top surface of the dielectric layer. Th method further includes modifying a sidewall of the metallic hardmask opening by adding non-metal atoms into the metallic hardmask. The method further includes depositing a conductive material in the metallic hardmask opening.

Method of making a semiconductor device and semiconductor device

A wafer having a first region and a second region is provided. A first topography variation exists between the first region and the second region. A first layer is formed over the first region and over the second region of the wafer. The first layer is patterned. A patterned first layer causes a second topography variation to exist between the first region and the second region. The second topography variation is smoother than the first topography variation. A second layer is formed over the first region and the second region. At least a portion of the second layer is formed over the patterned first layer.

Improving surface topography by forming spacer-like components

A method of making a dual damascene interconnect includes operations of depositing a metal hardmask over a dielectric layer; etching a metal hardmask opening in the metal hardmask to expose a top surface of the dielectric layer; etching at least one interconnect opening in the dielectric layer, to expose a top surface of a base conductive layer; modifying a sidewall of the metal hardmask opening; and depositing a conductive material in the metal hardmask opening and the at least one interconnect opening.

Poisoned metal layer with sloped sidewall for making dual damascene interconnect

Surface topography by forming spacer-like components

A semiconductor structure includes a substrate having a first region and a second region being adjacent each other; a first patterned layer formed on the substrate, wherein the first patterned layer includes first features in the first region, wherein the second region is free of the patterned layer; and a first guard ring disposed in the second region and surrounding the first features, wherein the first guard ring includes a first width Wand is spaced a first distance Dfrom the first features, Wbeing greater than D

Integrated circuit structure with guard ring

A method includes forming a patterned layer on a substrate having a first region and a second region being adjacent each other. The patterned layer includes first features in the first region. The second region is free of the patterned layer. The method further includes forming a material layer on the patterned layer and the substrate; forming a first guard ring disposed in the second region and surrounding the first features; forming a flowable-material (FM) layer over the material layer; forming a patterned resist layer over the FM layer, wherein the patterned resist layer includes a plurality of openings; and transferring the plurality of openings to the material layer.

Method of planarizating film

A light-emitting element, includes a substrate; a light-emitting stack formed on the substrate, including a triangular upper surface parallel to the substrate, having three sides and three vertexes; a first electrode formed on the light-emitting stack and located near a first vertex of the three vertexes of the triangular upper surface; and a second electrode formed on the light-emitting stack; including two second electrode pads respectively located near other two vertexes of the three vertexes; and a second electrode extending part extending from the second electrode pads, disposed along the three sides of the triangular upper surface.

Light-emitting diode device

An aggregation of semiconductor devices comprises a first layer, a second layer adhered to the first layer, and a plurality of semiconductor devices arranged between the first layer and the second layer to form a shape, wherein the shape comprises a curve and a mark, and the first layer is flexible.

Aggregation of semiconductor devices and the method thereof

A method includes forming a first photo resist layer over a base structure and a target feature over the base structure, performing an un-patterned exposure on the first photo resist layer, and developing the first photo resist layer. After the step of developing, a corner portion of the first photo resist layer remains at a corner between a top surface of the base structure and an edge of the target feature. A second photo resist layer is formed over the target feature, the base structure, and the corner portion of the first photo resist layer. The second photo resist layer is exposed using a patterned lithography mask. The second photo resist layer is patterned to form a patterned photo resist.

Lithography process on high topology features

A light-emitting element, includes a substrate; a first light-emitting stack formed on the substrate, including a triangular upper surface parallel to the substrate, and wherein the triangular upper surface has three sides and three vertexes; a first electrode formed on the first light-emitting stack and located near a first side of the three sides of the triangular upper surface; and a second electrode formed on the first light-emitting stack; including a second electrode pad near a first vertex of the three vertexes; and a second electrode extending part extending from the second electrode pad in two directions, disposed along other two sides of the three sides to surround the first electrode and stopping at the first side to form an opening.

A method of manufacturing an aggregation of semiconductor devices comprising the steps of providing a first layer; sequentially addressing and adhering a plurality of semiconductor devices to the first layer to form a shape having a curve; providing a second layer; and adhering the second layer to the first layer.

A method of fabricating integrated circuit devices is provided. The method includes forming a plurality of spaced integrated circuit dies on a semiconductor wafer and forming a dedicated test die on the semiconductor wafer adjacent the plurality of spaced integrated circuit dies, the dedicated test die including a test structure having a first width when viewed in a top view and being operable to generate wafer evaluation data. Further, the method includes forming a scribe line region interposed between the plurality of spaced integrated circuit dies, the scribe line region having a second width defined by a distance between adjacent integrated circuit dies when viewed in a top view, the second width being smaller than the first width, and the scribe line region being free of test structures.

Test structure placement on a semiconductor wafer

Growing community of inventors

Tainan, Taiwan

Chun-Chang Chen