Silicon Integrated Systems Corporation

Chun-An Tu

Chih-Yu Chang

Wei-Feng Lin

Hung-Ju Huang

Hung-Ta Pai

Hao-Luen Tien

Ming-Huan Lu

Chien-Chou Cheng

Ming-huan Lu

Tsung-chi Hsu

Ching-chang Shih

Shang-Yi Chen

A method for analyzing power noise and method for reducing the same are disclosed, wherein the present invention is utilized in an IC design process. First, a DC analysis is performed with a related IC design by utilizing computer aided design (CAD) software and circuit simulation software for obtaining a power network model of the IC design. Then, the power network model is defined as being composed of a plurality of unit blocks. After analysis, the quantity and type, etc., of components connected electrically to each of the unit blocks are recognized and are regarded as component reference data of each of the unit blocks. Afterwards, according to the component reference data of each of the unit blocks, the voltage drop (IR drop) occurring in operation for each of the unit blocks is evaluated and obtained by utilizing an equivalent circuit constructed by components that are connected electrically to each of the unit blocks. Therefore, the voltage consumption and distribution in each region of the power network model are obtained, so that at least one appropriate capacitor can be placed on proper locations of the power network model, to compensate the voltage drop caused by the IC design components while in operation, and to decrease the power noise in the IC design.

Method for analyzing power noise and method for reducing the same

A transmission circuit has a dispatching circuit and a calculating circuit. The transmission circuit is between a processing circuit and a memory controller. The processor is connected to the dispatching circuit via a first signal line. The dispatching circuit is connected to the calculating circuit via a second signal line. The calculating circuit is connected to the memory controller via a third signal line. Besides, a fast signal line is provided for connecting the dispatching circuit and the memory controller. During operation, the processing circuit transmits a data stream to the dispatching circuit. The dispatching circuit checks whether a speed-up condition is satisfied. If the speed-up condition is not satisfied, the data stream follows a conventional path through the calculating circuit. If the speed-up condition is satisfied, the data stream is directly transmitted to the memory controller and such design increases the performance of the transmission circuit.

Transmission circuit and manufacture method for the same

A partially embedded decoupling capacitor is provided as an integral part of a semiconductor chip for reducing delta-I noise. The semiconductor chip includes a plurality of embedded metal layers, a passivation layer formed above the plurality of embedded metal layers as a topmost layer of the semiconductor chip, and a plurality of bonding pads disposed on the passivation layer. A surface planar metal pattern is formed on the passivation layer and electrically connected to one of the plurality of embedded metal layers through one of the plurality of bonding pads or a via hole opened on the passivation layer. For example, the surface planar metal pattern may be connected to a power layer or a ground layer of the semiconductor chip. Therefore, the partially embedded decoupling capacitor is made up of the surface planar metal pattern as an electrode, others of the plurality of embedded metal layers as opposite electrodes, and the passivation layer sandwiched therebetween as a dielectric layer. Since connected to one of the plurality of embedded metal layers, the surface planar metal pattern further serves as a heat sink for dissipating heat directly from the inside of the semiconductor chip.

Semiconductor chip with partially embedded decoupling capacitors

An apparatus automatically determines an operating frequency of an integrated circuit (IC) chip that has a built-in self-test (BIST) unit to test the chip. The apparatus includes a clock generator and a frequency determination unit. The clock generator provides a test clock to the IC chip. The frequency determination unit sets the clock generator to generate the test clock and determines the operating frequency in accordance with a test result produced from the BIST unit. The frequency determination unit also enables the BIST unit to test the IC chip. Specifically, the frequency determination unit tunes a frequency value based on the test result, and sets the clock generator to generate the test clock corresponding to the tuned frequency value. Accordingly, the apparatus determines the highest frequency passing the built-in self-test, and sets the highest frequency for the IC chip as its operating frequency.

Apparatus and method for automatic determination of operating frequency with built-in self-test

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Tainan, Taiwan

Chun-An Tu