Samsung Electronics Co., Ltd.

Chulseung Lee

Choongeui Lee

Soon Suk Hwang

Kyuwook Han

Daehyun Kim

Seonghoon Woo

Hyungjin Kim

Taesung Lee

Jake Eu

Jonghyun Jang

A memory controller for a memory device, the memory controller including: a command generator configured to generate a command signal based on a system clock signal, and to generate phase difference information for the command signal; and a memory interface configured to receive the command signal and the phase difference information from the command generator, to adjust a timing of the command signal based on the phase difference information, and transmit the command signal of which the timing is adjusted as a timing adjusted command signal to the memory device.

Memory controller for a memory device

A storage device includes a nonvolatile memory device, and a controller that reads first data from the nonvolatile memory device. When a number of first errors of the first data is not smaller than a first threshold value, the controller determines whether the first errors include timing errors arising from a variation of signal transmission timings between the nonvolatile memory device and the controller and performs a retraining operation on the signal transmission timings when the first errors include the timing errors.

Storage device and operating method of storage device

A memory controller configured to control a non-volatile memory device includes: a signal generator configured to generate a plurality of control signals comprising a first signal and a second control signal; a core configured to provide a command for an operation of the non-volatile device; and a controller interface circuit configured to interface with the non-volatile memory device, wherein the controller interface circuit comprises a first transmitter connected to a first signal line and a second signal line; and a first receiver connected to the first signal line, and the first control signal and the second control signal are respectively transmitted to the non-volatile memory device through the first signal line and the second signal line.

Memory controller, storage device and memory system

A storage device includes a first memory device, a second memory device, and a controller. The first memory device and the second memory device share the same channel to communicate with the controller. Communication between the first memory device and the controller and communication between the second memory device and the controller are mutually exclusive. When the controller receives a read request directed to the second memory device while the controller processes a direct memory access (DMA) operation directed to the first memory device, the controller suspends the DMA operation and transmits a read command associated with the read request to the second memory device.

Storage device temporarily suspending internal operation to provide short read response time for read request from host

A storage device includes a plurality of nonvolatile memory devices each exchanging data by using a data strobe signal and a data signal, and a storage controller categorizing the plurality of nonvolatile memory devices into a plurality of groups and performing training in units of the plurality of groups. The storage controller performs data training on a first nonvolatile memory device selected in a first group of the plurality of groups and sets a delay of a data signal of a second nonvolatile memory device included in the first group by using a result value of the data training for the first nonvolatile memory device.

Storage device and data training method thereof

A data training method of a storage device, which includes a storage controller and a nonvolatile memory device, includes transmitting a read training command to the nonvolatile memory device, receiving a first training pattern output from the nonvolatile memory device in response to the read training command, receiving a second training pattern output from the nonvolatile memory device in response to the read training command, comparing the received first training pattern and the received second training pattern with a reference pattern, and determining a read timing offset of the storage controller depending on the comparison result.

Data training method of storage device

Disclosed is a storage device. The storage device includes a nonvolatile memory device that receives write data based on a data strobe signal and a data signal and outputs read data based on the data strobe signal and the data signal, and a controller that performs a training operation for training the nonvolatile memory device to align the data signal and the data strobe signal. The controller detects a left edge of a window of the data signal for the training operation. The controller determines a center of the window by using the detected left edge and unit interval length information of the data signal or determines a start point of a detection operation for detecting a right edge of the window by using the detected left edge and the unit interval length information.

A storage device includes first and second nonvolatile memory groups that respectively include first and second nonvolatile memory chips, a memory controller connected to the first and second nonvolatile memory groups in common through input/output lines and at least one control line, and a group select circuit connected to the memory controller through the at least one control line and chip enable lines. The group select circuit is connected to the first and second nonvolatile memory groups through a plurality of first and second chip enable lines, respectively. The group select circuit, in response to receiving a control signal through the at least one control line, is configured to transmit chip enable signals to a selected memory group among the first nonvolatile memory group and the second nonvolatile memory group through selected chip enable lines among the first chip enable lines and the second chip enable lines.

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Seoul, South Korea

Chulseung Lee