Cortina Systems Corporation

Azanda Network Devices, Inc.

Chulanur Ramakrishnan

Bidyut Parruck

Joseph Nguyen

A multi-service segmentation and reassembly (MS-SAR) integrated circuit is disposed on a line card in a router or switch. The MS-SAR can operate in an ingress mode so that it receives packet and/or cell format data and forwards that data to either a packet-based or a cell-based switch fabric. The MS-SAR can also operate in an egress mode so that it receives data from either a packet-based or a cell-based switch fabric and outputs that data in packet and/or cell format. The MS-SAR has a data path through which many flows of different traffic types are processed simultaneously. Each flow is processed by functional blocks along the data path in accordance with one of several application types, the application type for a flow being predetermined by the host processor of the router or switch. Segmentation, reassembly and partitioning techniques are disclosed that reduce costs and facilitate high-speed operation.

Multi-service segmentation and reassembly device that is operable in an ingress mode or in an egress mode

Multi-service segmentation and reassembly device that maintains only one reassembly context per active output port

Multi-service segmentation and reassembly device operable with either a cell-based or a packet-based switch fabric

Backpressuring using a serial bus interface and a status switch cell

Multi-service segmentation and reassembly device involving multiple data path integrated circuits

Multi-service segmentation and reassembly device that maintains reduced number of segmentation contexts

A method for dynamically allocating bandwidth among ATM cells and packets scheduled for output from an aggregation multiplexer of a transport-layer device configured to multiplex both ATM cells and packets onto the same channel of an optical fiber. The method includes local control and relative priority lookup of incoming ATM cells and packets to support output decision. When compared to currently employed methods, the required level of coordination with the receiving circuit for dynamic bandwidth allocation is substantially lower, thereby reducing operational complexity for network operators and latency for critical data when reallocating bandwidth.

Methods and apparatus for dynamically allocating bandwidth between ATM cells and packets

Multi-service segmentation and reassembly device with a single data path that handles both cell and packet traffic

Using an embedded indication of egress application type to determine which type of egress processing to perform

A technique for disguising ATM cells as ATM cell-containing packets within a routing facility to permit the packet-only switch to also handle switching of the ATM cells. The technique has wide applications within the backbone infrastructure, Wide Area Networks, Metro Area Networks, Local Area Networks, and particularly within a routing facility to handle high speed traffic. The technique can receive both ATM cells and packets for switching via a single channel or optical fiber or receive ATM cells and packets via two separate channels or two separate fibers. The ability to handle both ATM cell and packet switching allows packet-only routers to handle ATM traffic, thereby reducing the cost of the switching infrastructure for network operators.

Routers for switching ATM cells in a packet-like manner using a packet switch

An architecture for transmitting both ATM cells and data packets via a single optical fiber and for receiving ATM cells and data packets via a single optical fiber. The architecture includes both a transmission convergence device (TCD) circuit and a segmentation-and-reassembly (SAR) circuit and is implemented as integrated circuits, preferably as part of a router to eliminate the need for a SONET multiplexer.

Circuits for combining ATM and packet data on an optical fiber

A processor-based architecture having a processor for facilitating transmission between an ATM port, a first packet port, and a second packet port. The processor-based architecture includes random access memory and a processor coupled to the random access memory and configured to receive ATM cells from the ATM port and first packets from the first packet port and for outputting second packets containing information from both the ATM cells and the first packets on the second packet port. The processor-based architecture includes segmentation-and-reassembly to facilitate bi-directional packet-to-ATM translation functionality. In one embodiment, the processor-based architecture is implemented on a single card and includes dynamic traffic management between ATM and packet traffic.

PROCESSOR-BASED ARCHITECTURE FOR FACILITATING INTEGRATED DATA TRANSFER BETWEEN BOTH ATM AND PACKET TRAFFIC WITH A PACKET BUS OR PACKET LINK, INCLUDING BIDIRECTIONAL ATM-TO-PACKET FUNCTIONALLY FOR ATM TRAFFIC

An integrated ATM/packet segmentation-and-reassembly engine for handling both packet and ATM input data and outputting packets containing information from both the packet and ATM input data. The integrated ATM/packet segmentation-and-reassembly engine is also configured for receiving packets containing information destined for transmission as ATM cells and information destined for transmission as packets, perform the segregation function and segmentation function on the information destined for transmission as ATM cells in order to output both ATM cells and packets. Architecture includes the ability to output both ATM cells and packets on a single optical fiber.

Growing community of inventors

Saratoga, CA, United States of America

Chulanur Ramakrishnan