Samsung Electronics Co., Ltd.

Chul-woo Park

Hong-Sun Hwang

Jong-Pil Son

Hak-soo Yu

Young-Soo Sohn

Sang-beom Kang

Jae-Youn Youn

Uk-Song Kang

Kwang-il Park

Su-a Kim

Chan-Kyung Kim

Ho-jung Kim

Yun-sang Lee

Hyun-Ho Choi

Hyung-Rok Oh

In-gyu Baek

Hoi-ju Chung

Joo-sun Choi

Dong-hyun Sohn

Dong-seok Kang

Hye-Jin Kim

Sua Kim

Tae-young Kim

Seong-Jin Jang

Sung-chul Lee

Sang-Uhn Cha

Seung-eon Ahn

Young-Hyun Jun

Young-Pil Kim

Sei-jin Kim

Seong-young Seo

Soo-Ho Cha

Sang-Yun Kim

Si-Hong Kim

Hyo-jin Choi

Jong-wan Kim

Dong-Hyun Sohn

Hyung-rock Oh

Yeong-taek Lee

Chang-jung Kim

Jung-Hwan Choi

Jin-Young Kim

Jung-Bae Lee

Ki-Whan Song

In-kyeong Yoo

Kyo-Min Sohn

Won-Seok Lee

Kwan-Young Oh

Dae-Jeong Kim

Kee-Won Kwon

Won-Il Bae

Sung-Hyun Lee

Eun-sung Seo

Joo-Sun Choi

Dong-Soo Kang

Dae-Sun Kim

Kyoung-Heon Jeong

Jun-Hee Yoo

Sung-Min Ryu

Cheol-Heui Park

A memory device performing an internal copy operation is provided. The memory device may receive a source address, a destination address, and page size information together with an internal copy command, compares the source address with the destination address, and performs an internal copy operation. The internal copy operation may be an internal block copy operation, an inter-bank copy operation, or an internal bank copy operation. The internal copy operation may be performed with respect to one-page data, half-page data, or quarter-page data, based on the page size information. The memory device may output as a flag signal a copy-done signal indicating that the internal copy operation has been completed.

Memory device that performs internal copy operation

A magnetic random access memory (MRAM), and a memory module, memory system including the same, and method for controlling the same are disclosed. The MRAM includes magnetic memory cells configured to change between at least two states according to a magnetization direction, and a mode register supporting a plurality of operational modes.

Spin transfer torque magnetic random access memory for supporting operational modes with mode register

The memory device includes a memory array, control logic and a recovery circuit. The memory array has a first region configured to store data, a second region configured to store a portion of fail cell information, and a third region configured to store recovery information. The fail cell information identifies failed cells in the first region, and the recovery information is for recovering data stored in the identified failed cells. The control logic is configured to store the fail cell information, to transfer the portion of the fail cell information to the second region of the memory array, and to determine whether to perform a recovery operation based on address information in an access request and the portion of the fail cell information stored in the second region. The access request is a request to access the first region. The recovery circuit is configured to perform the recovery operation.

Memory device capable of quickly repairing fail cell

A memory system includes at least one memory device and a memory controller. The at least one memory device includes a refresh request circuit that generates refresh request signals at timings based on data retention times of memory cells, such as based on individual data retention times of a memory cell row. The memory controller schedules operation commands for the at least one memory device in response to the received refresh request signals.

Memory devices providing a refresh request and memory controllers responsive to a refresh request

Provided are a memory device and a memory module, which perform both an ECC operation and a redundancy repair operation. The memory device repairs a single-bit error due to a 'fail' cell by using an error correction code (ECC) operation, and also repairs the 'fail' cell by using a redundancy repair operation when the &#x2018;fail&#x2019; cell is not repairable by the ECC operation. The redundancy repair operation includes a data line repair and a block repair. The ECC operation may change a codeword corresponding to data per one unit of memory cells including the &#x2018;fail&#x2019; cell, and may also change the size of parity bits regarding the changed codeword.

Memory device for performing error correction code operation and redundancy repair operation

A semiconductor memory device may include a cell array comprising a plurality of memory cells, each memory cell connected to a word line and a bit line, the cell array divided into a plurality of blocks, each block including a plurality of word lines, the plurality of blocks including at least a first defective block; a nonvolatile storage circuit configured to store address information of the first defective block, and to output the address information to an external device; and a fuse circuit configured to cut off an activation of word lines of the first defective block.

Semicondutor memory device and memory system including the same

A semiconductor memory device includes a memory cell array and a test circuit. The test circuit reads data stream from the memory cell array, configured to, on comparing bits of each first unit in the data stream, compares corresponding bits in the first units as each second unit and outputs a fail information signal including pass/fail information on the data stream and additional information on the data stream, in a test mode of the semiconductor memory device.

Semiconductor memory devices, memory systems including the same and methods of operating the same

A memory device having an error notification function includes an error correction code (ECC) engine detecting and correcting an error bit by performing an ECC operation on data of the plurality of memory cells, and an error notifying circuit configured to output an error signal according to the ECC operation. The ECC engine outputs error information corresponding to the error bit corresponding to a particular address corrected by the ECC operation. The error notifying circuit may output the error signal when the particular address is not the same as any one of existing one or more failed addresses.

Memory device having error notification function

A use time managing method of a semiconductor device may include (1) measuring an amount of accumulated operation time of the semiconductor device and when the amount is reached to a predetermined value, generating a unit storage activation signal; (2) repeating step (1) to generate one or more additional unit storage activation signals, thereby generating a plurality of unit storage activation signals, wherein the predetermined values are different for each repeating step; (3) storing data indicating each occurrence of generating the unit storage activation signals; and (4) detecting use time of the semiconductor device based on the cumulatively stored data.

Method of use time management for semiconductor device and semiconductor device including use time managing circuit

A memory device includes a memory cell array, an intensively accessed row detection circuit, and a refresh control circuit. The memory cell array includes a plurality of memory cell rows. The intensively accessed row detection circuit generates an intensively accessed row address indicating an intensively accessed memory cell row among the plurality of memory cell rows based on an accumulated access time for each of the plurality of memory cell rows. The refresh control unit preferentially refreshes neighboring memory cell rows adjacent to the intensively accessed memory cell row indicated by the intensively accessed row address when receiving the intensively accessed row address from the intensively accessed row detection unit. The memory device effectively reduces a rate of data loss.

Memory device and memory system having the same

A method of operating a volatile memory device includes storing address information of weak cell rows. According to some examples, after writing to a weak cell row, a refresh operation is performed on the weak cell row within a predetermined time. According to some examples, the writing operation to a weak cell row may be performed with a longer write recovery time than a write recovery time to normal cell rows.

Method of operating a volatile memory device and a memory controller

At least one refresh without scrubbing is performed on a corresponding portion of the memory device with a first frequency. In addition, at least one refresh with scrubbing is performed on a corresponding portion of the memory device with a second frequency less than the first frequency. Accordingly, refresh operations with data scrubbing are performed to prevent data error accumulation. Furthermore, refresh operations without data scrubbing are also performed to reduce undue power consumption from the data scrubbing.

Method and apparatus for refreshing and data scrubbing memory device

Growing community of inventors

Yongin-si, South Korea

Chul-woo Park