Samsung Electronics Co., Ltd.

Chul-Sung Park

Hyang-Ja Yang

Yong-Hwan Noh

Jang-Woo Ryu

Gong-Heum Han

Tae-Seong Jang

Chi-sung Oh

Young-Dae Lee

Hoi-ju Chung

Joo-sun Choi

Eunsung Seo

Byung-gil Jeon

Byong-Kwon Lee

Young-Seung Kim

Myung-Han Choi

Jung-Bae Lee

Tae-Young Oh

Jae-Wook Lee

Young-Hun Seo

Sang-Bo Lee

Seung-Min Lee

Young-Tae Kim

Nam-Seog Kim

Duk-Ha Park

Woo-Seop Jeong

Dong-hyun Sohn

Chang-Yong Lee

Ki-Chul Chun

Gyu-Chul Kim

Soo-Hwan Kim

Hui-Kap Yang

Chan-yong Lee

Min-soo Jang

Kang-Sik Cho

Yong-hwan Noh

Cheol-Shin Kwak

Hong-Kyun Kim

Byong-kwon Lee

A semiconductor memory device comprises a memory cell array and a data inversion circuit. The data inversion circuit is configured to receive a first unit data and a second unit data stored in the memory cell array through different first data lines, determine, while the first unit data is transmitted to a data input/output (I/O) buffer through a second data line, whether to the invert the second unit data based on a Hamming distance between the first unit data and the second unit data, and transmit the inverted or non-inverted second unit data to the data I/O buffer through the second data line.

Semiconductor memory device, memory system, and method using bus-invert encoding

A memory chip, a memory system, and a method of accessing the memory chip. The memory chip includes a substrate, a first storage unit, and a second storage unit. The first storage unit includes a plurality of first memory cells may have a first storage capacity of 2. The plurality of first memory cells may be configured to activate in response to a first selection signal. The second storage unit includes a plurality of second memory cells and may have a second storage capacity of 2. The plurality of second memory cells may be configured to activate in response to a second selection signal.

Memory chip, memory system, and method of accessing the memory chip

A method of operating a memory device includes: generating an internal read command in response to a received masked write command, the internal read command being generated one of (i) during a write latency associated with the received masked write command, (ii) after receipt of a first bit of masked write data among a plurality of bits of masked write data, and (iii) in synchronization with a rising or falling edge of a clock signal received with an address signal corresponding to the masked write command; reading, in response to the internal read command, a plurality of bits of data stored in a plurality of memory cells, the plurality of memory cells corresponding to the address signal; and storing, in response to an internal write command, the plurality of bits of masked write data in the plurality of memory cells.

Memory devices that perform masked write operations and methods of operating the same

A semiconductor memory device that may correct error data using an error correction circuit is disclosed. The semiconductor memory device may include a DRAM cell array, a parity generator, a nonvolatile memory cell array and an error correction circuit. The parity generator is configured to generate a first set of parity bits having at least one bit based on input data. The nonvolatile memory cell array may store the input data and the first set of parity bits corresponding to the input data, and to output first data corresponding to the input data, and a second set of parity bits corresponding to the first set of parity bits. The error correction circuit is configured to generate second data as corrected data based on the first data.

Semiconducotr memory device including non-volatile memory cell array

A semiconductor memory device includes multiple voltage generators. The memory device includes a first voltage generator for generating a first internal voltage based on a first power supply voltage, and a second voltage generator for generating a second internal voltage based on a second power supply voltage that is lower than the first power supply voltage. The first internal voltage is used as a driving voltage of a bit line sense amplifier in a core block including a memory cell array. The second internal voltage that is lower than the first internal voltage is used as a driving voltage of a peripheral circuit block other than the core block.

Memory device with multiple voltage generators

In one embodiment, the semiconductor device includes a memory array and a control architecture configured to control reading data from and writing data to the memory array. The control architecture is configured to receive data and a codeword location in the memory array, select one or more data units in the received data based on a data mask, read a codeword currently stored at the codeword location in the memory array, error correct the read codeword to generate a corrected read codeword, form a new codeword from the selected data units of the received data and data units in the corrected read codeword that do not correspond to the selected data units, and write the new codeword to the memory array.

Semiconductor memory devices, memory systems including the same and method of writing data in the same

Provided is a bit line sense amplifier source node control circuit of a semiconductor memory device. The sense amplifier source node control circuit may include a source driver connected between a source node of a sense amplifier and a sense amplifier driving signal line, for driving the source node of the sense amplifier to a set voltage level. The sense amplifier source node control circuit may also include: a floating circuit for floating the sense amplifier driving signal line in a set operating mode; and a controller connected in parallel with the source driver between the source node of the sense amplifier and the sense amplifier driving signal line, for controlling a level of the sense amplifier driving signal line in the set operating mode.

Circuit for controlling sense amplifier source node in semiconductor memory device and controlling method thereof

A memory device comprises at least two memory ranks sharing input/output lines, at least one mode register configured to store bits used to tune delays of data signals of the at least two ranks output through the input/output lines, a controller configured to determine tuning parameters for the data signals based on the stored bits in the at least one mode register, the tuning parameters comprising at least the delays of the data signals, and at least one nonvolatile memory disposed in at least one of the at least two memory ranks and configured to store the tuning parameters.

Memory system having memory ranks and related tuning method

A method of refreshing a semiconductor memory device includes performing a first refresh operation for memory cells included in a memory cell array, and determining whether a command other than a refresh command is applied to the semiconductor memory device in a refresh cycle of the first refresh operation. The method further includes continuing to perform the first refresh operation when a command other the refresh command is applied to the semiconductor memory device in one refresh cycle of the first refresh operation, and performing a second refresh operation when a command other than the refresh command is not applied to the semiconductor memory device in one refresh cycle of the first refresh operation. A refresh time of the second refresh operation is greater than a refresh time of the first refresh operation.

Semiconductor memory device including refresh control circuit and method of refreshing the same

A row address control circuit of a semiconductor memory device including dynamic memory cells includes a test mode setting unit, an address counter and a row address generating unit. The test mode setting unit is configured to provide a test mode signal that indicates whether a test operation is performed or not, in response to a test command; the address counter is configured to generate a first address that increases gradually; and the row address generating unit is configured to selectively choose one of the first address and a second address as a refresh address based on the test mode signal, the second address being externally provided.

Row address control circuit semiconductor memory device including the same and method of controlling row address

Provided are a level shifter and a semiconductor device having an OFF-chip driver (OCD) using the same. The level shifter includes a plurality of series connected logic gates receiving a first-state input signal having a first power supply voltage level and generating a level-shifted first-state output signal having a second power supply voltage level. The logic gates receive as power supply voltages at least one intermediate power supply voltage having at least one voltage level intermediate between the first power supply voltage level and the second power supply voltage level, and an intermediate power supply voltage applied to the present logic gate is equal to or higher than an intermediate power supply voltage applied to the previous logic gate.

Level shifter and semiconductor device having off-chip driver

A semiconductor memory device capable of synchronous/asynchronous operation and data input/output method thereof are provided. The semiconductor memory device includes a memory cell array, a peripheral circuit configured to write data to a cell in the memory cell array and to read data from the cell, and a bypass control unit configured to control a late write operation and a bypass operation of the peripheral circuit according to mode conversion of the semiconductor memory device. Accordingly, data coherency can be maintained. In addition, dummy cycle time that may occur during the mode conversion can be prevented by generating a mode conversion signal only in response to toggling of a clock signal.

Semiconductor memory device capable of synchronous/asynchronous operation and data input/output method thereof

There is provided a bit line voltage supply circuit for reducing leakage current flowing from bit lines to a memory cell without substantially deteriorating the performance of a semiconductor memory device. A bit line voltage switch applies a first supply voltage to a bit line pair in response to a first switch control signal, and applies a second supply voltage having a lower voltage than the first supply voltage to the bit line pair in response to a second switch control signal. A bit line voltage controller controls the first and second switch control signals so that the second supply voltage is supplied to the bit line pair during a standby mode, and the first supply voltage is supplied to the bit line pair when the semiconductor memory device changes from the standby mode to an operational mode for a predetermined time period.

Bit line voltage supply circuit in semiconductor memory device and voltage supplying method therefor

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Seoul, South Korea

Chul-Sung Park