Samsung Electronics Co., Ltd.

Chul-Sung Kim

Bon-Young Koo

Si-Young Choi

Byeong-Chan Lee

Sang-Jin Hyun

Hyo-Seok Choi

Young-Jin Noh

Sang-Woo Lee

Yu-Gyun Shin

Sang-Bom Kang

Jin-bum Kim

Jung-Woo Park

Deok-Hyung Lee

Dae-Yong Kim

Jong-Ryeol Yoo

Do-Sun Lee

Young-jin Noh

Sung-Kweon Baek

Joon-Gon Lee

Jeong-Ik Kim

Jung-Geun Jee

Chung-Hwan Shin

Jong-Ryol Ryu

Je-Hyung Ryu

Shigenobu Maeda

Woong Hee Lee

In-Soo Jung

Hun-Hyeoung Leam

Ja-hum Ku

Ja-Hum Ku

Ki-hyun Hwang

Young-Moon Choi

Jin-Hwa Heo

Ryuji Tomita

Deok-han Bae

Chang-Woo Sohn

Sung-kweon Baek

Do-hyun Lee

Chang-Hyun Lee

Ji-Hyun Kim

Kyung-Soo Kim

Ki-Hyun Hwang

Dong-Chan Kim

Dong-Ho Ahn

Hwi-Chan Jun

Hyoung-sub Kim

Jae-Yoon Yoo

Sug-hun Hong

Sug-Hun Hong

Soo-Geun Lee

In-Sang Jeon

Chul-Joon Choi

Kwang-Young Lee

Deok-Han Bae

Da-Il Eom

Tae-Wook Seo

Eung-joon Lee

Woo-Cheol Shin

Joo-Hyuk Chung

Jun-Ki Park

A method of forming a semiconductor device can be provided by forming an opening that exposes a surface of an elevated source/drain region. The size of the opening can be reduced and a pre-amorphization implant (PAI) can be performed into the elevated source/drain region, through the opening, to form an amorphized portion of the elevated source/drain region. A metal-silicide can be formed from a metal and the amorphized portion.

Semiconductor devices with shaped portions of elevated source/drain regions

Semiconductor devices are provided. A semiconductor device includes a substrate. The semiconductor device includes an isolation layer defining active portions of the substrate that are spaced apart from each other in a direction. The semiconductor device includes an epitaxial layer on the active portions. The semiconductor device includes a metal silicide layer on the epitaxial layer. Moreover, the semiconductor device includes a contact structure that only partially overlaps the metal silicide layer on the epitaxial layer. Related methods of forming semiconductor devices are also provided.

Semiconductor devices including contact structures that partially overlap silicide layers

An integrated circuit device includes a substrate, a gate structure, a spacer structure, a source/drain region, and a first contact structure. The substrate includes a fin-type active region. The gate structure intersects with the fin-type active region on the substrate, and has two sides and two side walls. The spacer structure is disposed on both side walls of the gate structure and includes a first spacer layer contacting at least a portion of both side walls of the gate structure and a second spacer layer disposed on the first spacer layer and having a lower dielectric constant than a dielectric constant of the first spacer layer. The source/drain region is disposed on both sides of the gate structure. The first contact structure is electrically connected to the source/drain region and includes a first contact plug disposed on the source/drain region and a first metallic capping layer disposed on the first contact plug.

Integrated circuit device

An integrated circuit device includes at least one fin-type active region, a gate line on the at least one fin-type active region, and a source/drain region on the at least one fin-type active region at at least one side of the gate line. A first conductive plug is connected to the source/drain region and includes cobalt. A second conductive plug is connected to the gate line and spaced apart from the first conductive plug. A third conductive plug is connected to each of the first conductive plug and the second conductive plug. The third conductive plug electrically connects the first conductive plug and the second conductive plug.

A semiconductor device may include a substrate including an NMOS region and a PMOS region, and having a protrusion pattern; first and second gate structures respectively formed on the NMOS region and the PMOS region of the substrate, crossing the protrusion pattern, and extending along a first direction that is parallel to an upper surface of the substrate; first and second source/drain regions formed on both sides of the first and second gate structures; and first and second contact plugs respectively formed on the first and second source/drain regions, wherein the first contact plug and the second contact plug are asymmetric. Methods of manufacturing are also provided.

Semiconductor device and method of fabricating the same

A semiconductor device includes an active fin partially protruding from an isolation pattern on a substrate, a gate structure on the active fin, a source/drain layer on a portion of the active fin adjacent to the gate structure, a source/drain layer on a portion of the active fin adjacent to the gate structure, a metal silicide pattern on the source/drain layer, and a plug on the metal silicide pattern. The plug includes a second metal pattern, a metal nitride pattern contacting an upper surface of the metal silicide pattern and covering a bottom and a sidewall of the second metal pattern, and a first metal pattern on the metal silicide pattern, the first metal pattern covering an outer sidewall of the metal nitride pattern. A nitrogen concentration of the first metal pattern gradually decreases according to a distance from the outer sidewall of the metal nitride pattern.

Semiconductor device including contact plug and method of manufacturing the same

An integrated circuit device including a substrate having at least one fin-shaped active region, the at least one fin-shaped active region extending in a first direction, a gate line extending on the at least one fin-shaped active region in a second direction, the second direction intersecting with the first direction, a conductive region on a portion of the at least one fin-shaped active region at one side of the gate line, and a contact plug extending from the conductive region in a third direction, the third direction being perpendicular to a main plane of the substrate, may be provided. The contact plug may include a metal plug, a conductive barrier film on the conductive region, the conductive barrier film surrounding a sidewall and a bottom surface of the metal plug, the conductive barrier film including an N-rich metal nitride film, and a metal silicide film between the conductive region and the conductive barrier film.

Integrated circuit device and method of fabricating the same

A method for fabricating a semiconductor device is provided. The method includes forming a gate electrode and a source or drain disposed at opposite sides of the gate electrode, forming an interlayer insulating layer covering the gate electrode and the source or drain, forming a contact hole exposing the source or drain in the interlayer insulating layer, forming a silicide layer on a bottom surface of the contact hole, and forming a spacer on sidewalls of the contact hole and an upper surface of the silicide layer.

Method for fabricating semiconductor device having a silicide layer

Methods of forming semiconductor devices with metal silicide using pre-amorphization implants

A method of fabricating a metal silicide layer includes forming a metal layer on a substrate, and forming a pre-metal silicide layer by reacting the substrate with the metal layer by performing a first annealing process on the substrate. The method also includes implanting silicon into the substrate using a gas cluster ion beam (GCIB) process, and changing the pre-metal silicide layer into a metal silicide layer by performing a second annealing process on the substrate.

Fabricating method of metal silicide layer, fabricating method of semiconductor device using the same and semiconductor device fabricated using the method

A method of fabricating a semiconductor includes providing a substrate having a first region and a second region defined therein, forming a first gate and a first source and drain region in the first region and forming a second gate and a second source and drain region in the second region, forming an epitaxial layer in the second source and drain region, forming a first metal silicide layer in the first source and drain region, forming an interlayer dielectric layer on the first region and the second region, forming a plurality of contact holes exposing the first metal silicide layer and the epitaxial layer while penetrating the interlayer dielectric layer, forming a second metal silicide layer in the exposed epitaxial layer, and forming a plurality of contacts contacting the first and second metal silicide layers by filling the plurality of contact holes.

Method of fabricating semiconductor device

A non-volatile memory device includes a dielectric layer between a charge storage layer and a substrate. Free bonds of the dielectric layer can be reduced to reduce/prevent charges from leaking through the free bonds and/or from being trapped by the free bonds. As a result, data retention properties and/or durability of a non-volatile memory device may be enhanced.

Methods of forming non-volatile memory devices

Growing community of inventors

Seongnam-si, South Korea

Chul-Sung Kim