Skhynix Inc.

Chul Moon Jung

Woongrae Kim

Yoonna Oh

Byeong Yong Go

Jeong Tae Hwang

Mi Hyun Hwang

Jae Hwan Seo

Sang Kwon Lee

Saeng Hwan Kim

Joo Hyeon Lee

Kwi Dong Kim

Mun Phil Park

Man Keun Kang

Sung Nyou Yu

Seok Cheol Yoon

Uk Song Kang

Hoiju Chung

A memory device includes: a rate control circuit configured to: generate a refresh counting value based on a refresh management command and an internal target refresh command, and generate a rate control signal by comparing the refresh counting value with a target value corresponding to temperature information; and a target command issuing circuit configured to: set a target number according to the rate control signal, and issue the internal target refresh command whenever a number of inputs of a normal refresh command reaches the target number.

Memory device and memory system for performing target refresh operation, and operation method thereof

A semiconductor memory device includes: a memory cell region including a plurality of cell mats in each of which a plurality of rows are disposed, each row coupled to normal cells and row-hammer cells; a repair control circuit suitable for generating a pairing flag denoting whether a cell mat in which an active row corresponding to an active address is disposed, is repaired with another cell mat; and a refresh control circuit suitable for: selecting, when an active command is inputted, a sampling address based on first and second data read from the row-hammer cells of the active row, refreshing, when a target refresh command is inputted, one or more adjacent rows to a target row corresponding to the sampling address, and selectively refreshing, when the target refresh command is inputted, one or more adjacent rows to a paired row of the target row according to the pairing flag.

Semiconductor memory device and operating method thereof

An operation method of a memory may include entering a self-refresh mode, increasing a level of a back-bias voltage in response to entering the self-refresh mode, performing self-refresh operations in a first cycle, confirming that the back-bias voltage reaches a level of a first threshold voltage, and performing the self-refresh operations in a second cycle longer than the first cycle in response to the confirmation.

Memory and operation method thereof

A fuse latch of a semiconductor device including PMOS transistors and NMOS transistors includes a data transmission circuit configured to transmit data to a first node and a second node in response to a first control signal, a latch circuit configured to latch the data received from the data transmission circuit through the first node and the second node, and a data output circuit configured to output the data latched by the latch circuit in response to a second control signal. NMOS transistors contained in the data transmission circuit, the latch circuit, and the data output circuit may be formed in first, fourth, and fifth active regions, PMOS transistors are formed in second and third active regions, and the first to fifth active regions are sequentially arranged in a first direction.

Fuse latch of semiconductor device for latching data of a repair fuse cell

A method for operating a memory includes: receiving an active command and a row address; confirming that a portion of columns of a first row corresponding to the row address is replaced with a portion of columns of a second row; activating the first row and the second row; confirming activation of a random pulse; randomly selecting one among the row address corresponding to the first row and a row address corresponding to the second row in response to the activation of the random pulse; and sampling the selected row address as a sampling address.

Memory and operation method of memory with repairing and random pulse generating capability

An integrated circuit includes: first and second pattern generation circuits generating first and second pattern signal for a sampling section; a first section control part generating a coarse section signal for a first section of the sampling section, according to the first pattern signal; a first filter part generating a first section extract signal by filtering the second pattern signal according to the coarse section signal; a second section control part generating a fine section signal for a second section of the sampling section, according to the first section extract signal; a second filter part generating a second section extract signal by filtering the second pattern signal according to the fine section signal; an output control circuit generating a sampling enable signal according to the first and second section extract signals; and a sampling circuit suitable for sampling an input signal according to the sampling enable signal.

Integrated circuit and memory device including sampling circuit

A memory device may include: a memory bank comprising a plurality of memory blocks, each divided into a normal area and a row hammer area, a command control circuit suitable for performing an access operation on the normal area in response to an active command, an internal command generation circuit suitable for generating an internal command in response to a precharge command, a target address generation circuit suitable for saving a count for each logic level combination of a received address in the row hammer area by performing an access operation on the row hammer area in response to the internal command, and setting an address corresponding to the count as a target address when the count satisfies a preset condition, and a refresh control circuit suitable for controlling a smart refresh operation on the target address.

Memory device for performing smart refresh operation by counting received address

A method for operating a memory system includes: collecting, by a memory controller, information on rows that are determined as row-hammer-attacked in a memory by the memory controller; collecting, by the memory, information on rows that are determined as row-hammer-attacked by the memory; confirming, by the memory, that the row collected by the memory controller is the same as the row collected by the memory; and resetting, by the memory, information on the row collected by the memory which is the same as the row collected by the memory controller in response to the confirmation.

Memory, memory system and operation method of memory system

A memory system includes: an address scrambler suitable for scrambling an address based on a scrambling rule to generate a scrambled address; a memory core including a plurality of memory cells and suitable for storing data in memory cells designated by the scrambled address; and a scramble control circuit suitable for changing the scrambling rule in response to satisfaction of an attack condition.

Memory system and operation method of memory system

A semiconductor memory device comprises: first storage logic configured to store, as first addresses, 'K' addresses having different values among input addresses applied during the enable period of a reference signal, second storage logic configured to store, as second addresses, ‘L’ addresses corresponding to a time point at which the enable period of the reference signal is ended among the input addresses, an order controller configured to determine a first output order of each of the first addresses based on a number of times each of the first addresses is repeatedly input, and to determine a second output order for outputting mixed addresses obtained by mixing the first addresses based on the first output order and the second addresses together, and refresh operation logic configured to apply the mixed addresses according to the second output order, to a target refresh operation.

Apparatus and method for performing target refresh operation

A semiconductor device may include a fuse array configured to output fuse data. The semiconductor device may include a latch circuit configured to store the fuse data during an enabled section of a dummy boot-up signal, output the stored fuse data as a fuse data information signal during a disabled section of the dummy boot-up signal, and fix the fuse data information signal to a specific level during the enabled section of the dummy boot-up signal regardless of the stored fuse data.

Semiconductor device and method of operating the same

A refresh control device for reducing power consumption during a target row refresh operation is disclosed. The refresh control device includes a refresh address generator configured to generate a refresh address by selecting any one of a target row refresh address and a normal refresh address according to a target row refresh flag signal, an address control signal generator configured to generate a multiple address control signal in response to the target row refresh flag signal and a multiple refresh signal, and a final refresh address generator configured to generate a plurality of final refresh addresses from the refresh address in response to the multiple address control signal.

Refresh control device

A semiconductor system may include a first semiconductor device and a second semiconductor device. The first semiconductor device may output a clock signal, a test mode signal and command address signals. The second semiconductor device may repeatedly write and read out data into and from a plurality of memory cells sequentially selected by addresses that are sequentially counted or may repeatedly write and read out the data into and from specific memory cells selected by a specific address among the addresses, according to the clock signal and the command address signals in response to the test mode signal.

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Icheon-si, South Korea

Chul Moon Jung