Samsung Electronics Co., Ltd.

Chul-Min Jung

Min-Chul Chung

Young-Dae Lee

Young-Ho Suh

Jeong-hee Lee

Hee-Choul Park

Uk-rae Cho

Eun-Cheol Kim

Seung-Kweon Yang

Ig-Soo Kwon

Hee-chul Park

Hee-choul Park

Kee-sik Ahn

A self-resetting circuit includes a logic circuit operative to transition an output signal from a first logic state to a second logic state responsive to a first logic state transition of an input signal, along with a bistable reset circuit coupled to the logic circuit and operative to be triggered by the transition of the output signal from the first logic state to the second logic state to reset the output signal to the first logic state within a first predetermined interval following the transition of the output signal from the first logic state to the second logic state, and to be armed by a second logic state transition of the input signal next succeeding the first logic state transition, wherein the reset circuit is armed within a second predetermined interval following the second transition that is less than the first predetermined interval. Related operating methods are also discussed.

Self-resetting logic circuits and method of operation thereof

Disclosed is a semiconductor memory device including a redundancy controller. The redundancy controller is structured using pass gate logic, dynamic inverter circuits, and a true/complement decoder scheme. The redundancy controller includes first and second redundancy enable circuits corresponding respectively to first and second redundant columns. A first and second fuse boxes are coupled respectively to the first and second redundancy enable circuits. The first and second fuse boxes each include a fuse box circuit corresponding to the column address signals and a fuse element. Each fuse box circuit receives a corresponding pair of true and complement column address signals and manipulates the true and complement column address signals responsive to the fuse element. A first decoding means decodes the manipulated versions of the true and complement column address signals and generates first and second true decoded pulse signals and first and second complement decoded pulse signals. A second decoding means decodes the manipulated versions of the true and complement column address signals and generates third and fourth true decoded pulse signals and third and fourth complement decoded pulse signals. A sense amplification control signal generating means produces the sense amplification control signal responsive to the first, second, third, and fourth true decoded pulse signals and the first, second, third, and fourth complement decoded pulse signals. A row select signal generating means produces the row select signal responsive to first, second, third, and fourth true decoded pulse signals. The above-described redundancy controller improves the redundancy speed.

Semiconductor memory device with true/complement redundancy scheme

A semiconductor memory device for providing a burst mode control signal. The semiconductor memory device includes a first logic circuit for generating a driving signal in response to a first logic level of an externally input write and read control signal and an externally input chip enable signal, a plurality of transition registers for respectively changing the driving signal in synchronization with a first edge of a clock signal to generate changed driving signals, and a second logic circuit for generating the burst mode control signal generated by the logic combination of the changed driving signals in response to a read latency control signal.

Semiconductor memory device for providing burst mode control signal,

A scalable level shifter which performs at high-speeds and optimizes power consumption. The scalable level shifter receives an input signal and converts the input signal having a scalable voltage level to an output signal having a predetermined voltage level. The scalable level shifter includes a self-resetting circuit connected to an internal power supply for interrupting an internal current path responsive to output signal voltage variations corresponding to voltage transitions of the input signal.

Scalable level shifter for use in semiconductor memory device

Redundancy decoding systems and methods for integrated circuit memory devices synchronize a redundancy decoding signal to allow the redundancy decoding signal to be output during an enabling period and to prevent output of the redundancy decoding signal otherwise. In particular, a redundancy decoder is synchronized to an output buffer so that the redundancy decoder generates a redundancy decoding signal during a time period which is independent of the identity of the programmed address. Accordingly, high speed selection of a redundancy word line is provided in synchronism with the conventional word line selection, so that address skew and improper operation of the redundancy system relative to the normal word line selection system is prevented.

Synchronized redundancy decoding systems and methods for integrated

A level converter for use in a semiconductor memory device includes a level converting unit, a latch circuit and a blocking circuit. The level converting unit receives sensed first and second sensing voltages and a control clock and which provides level-converted first and second output voltages in correspondence with the first and second sensing voltage at first and second output nodes in response to the control clock. The latch circuit boosts a difference between the first and second output voltages provided at the first and second output nodes to be substantially equal to the level of a supply voltage in response to the application of the supply voltage. The blocking circuit controls the application of the supply voltage to the level converting unit and the latch circuit according to the control clock, in order to reduce current consumption due to the application of the supply voltage and to achieve a high operating speed.

Dynamic level converter of a semiconductor memory device

A gunn transceiver logic input circuit for use in a semiconductor memory device is capable of effectively inputting a signal having a small voltage difference. The gunn transceiver logic input circuit includes first and second input units which respectively input a GTL-level input signal and a GTL-level reference signal. First and second generating units with first and second level shifters respectively shift the GTL-level input signal and GTL-level reference signal to the ECL-level. An ECL buffer circuit compares the voltages between the ECL-level input signal and the ECL-level reference signal and generates first and second ECL-level output signals while maintaining a swing width of the GTL level signal.

Gunn transceiver logic input circuit for use in a semiconductor memory

Semiconductor integrated circuits, and more particularly an internal power-supply voltage supplier, can be adapted to high density memory devices, for providing a converted external power-supply voltage as an internal power-supply voltage having a desired potential. An internal power-supply voltage supplier receives a reference signal and an internal power-supply voltage signal and provides a semiconductor integrated circuit with an internal power-supply voltage having a desired voltage level by way of a driver, and comprises an offset generator connected to the driver, including two transistors having different width-length characteristics, for receiving the reference signal and the internal power-supply voltage signal and producing an offset corresponding to the received signals, the internal power-supply voltage is provided at a desired voltage level by the driver when the offset generator performs an offset operation.

Internal power-supply voltage supplier of semiconductor integrated

A semiconductor memory device which includes, in a first embodiment, a first PMOS transistor having a source electrode coupled to a signal transport line, a second PMOS transistor having a source electrode coupled to an inverted signal transport line, a drain electrode coupled to a gate electrode of the first PMOS transistor, and a gate electrode coupled to a drain electrode of the first PMOS transistor, a first current limiter connected between the drain electrode of the first PMOS transistor and a reference potential, a second current limiter connected between the drain electrode of the second PMOS transistor and the reference potential, a first constant current source connected between a supply voltage and the source electrode of the first PMOS transistor, and, a second constant current source connected between the supply voltage and the source electrode of the second PMOS transistor.

Semiconductor memory device

A level shifter and a data output buffer adapted for use in a semiconductor memory device including a memory cell for storing data, a sense amplifier for amplifying data read from the memory cell and generating an ECL-level output signal, and a level shifter for converting the ECL-level output signals into a CMOS-level signal, wherein the level shifter has a level shifting means receiving the ECL-level data signals, converting the input data to CMOS-levels, and outputting a result, and a delay for delaying the result so as to control its current consumption of the level shifter.

Level shifter and data output buffer having same

A data output circuit of a semiconductor memory device matches an equalizing level of voltages at data lines in a pair with a logic threshold voltage of data output buffers. The data output circuit having an equalizing transistor connected between first and second nodes connected to the outputs of a sense amplifier, includes a threshold voltage control circuit disposed between the sense amplifier and the data output buffers for allowing a threshold voltage of the data output buffers to match with the equalizing level of the voltages at the first and second nodes. The threshold voltage control circuit has the same structure and characteristics as that of the output buffers, so as to ensure that the logic threshold voltage of the data output buffers matches with the equalizing level of the voltages at the first and second nodes.

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Seoul, South Korea

Chul-Min Jung