Skhynix Inc.

Hynix Semiconductor Inc.

Industry-academic Cooperation Foundation, Yeungnam University

Chul Keun Yoon

Tae Min Kang

Dae Woong Lee

Min Kyu Kang

Gyu Jei Lee

Byoung Do Lee

Yu Hwan Kim

Dong Kil Shin

Jae Hyun Son

You Kyung Hwang

Jae-hyun Son

Yu Gyeong Hwang

A method includes providing a device under test, which includes a lower test layer and an upper test layer that is stacked on the lower test layer and includes an overhang protruding past an edge of the lower test layer by a predetermined length, fixing the lower test layer onto a mounting stage, and measuring adhesive force of an interlayer adhesive layer in a tensile mode by applying a load to a bottom surface of the overhang of the upper test layer in a first direction. An apparatus includes a mounting stage fixing the device under test, a load applying tip applying the load to the bottom surface of the overhang, a location adjuster adjusting a distance between the device under test and the load carrying tip, a load cell detecting a magnitude of the applied load, and a controller controlling the location adjuster and the load cell.

Method of measuring an adhesive force of interlayer adhesive layer in tensile mode for stacked semiconductor device and apparatus for measuring the same

A stack package having a plurality of stacked chips includes first voltage dropping units respectively formed in the plurality of chips, the first voltage dropping units are electrically coupled by a first line; second voltage dropping units respectively formed in the plurality of chips, the second dropping units are electrically coupled by a second line; first signal generation units respectively formed in the plurality of chips, each of the first signal generation units is connected to an output node of the first voltage dropping units, respectively; and second signal generation units respectively formed in the plurality of chips, each of the second signal generation units is connected to an input node of the second voltage dropping units, respectively.

Stack package and method for selecting chip in stack package

A stack semiconductor package includes a first insulation member having engagement projections and a second insulation member formed having engagement grooves into which the engagement projections are to be engaged. First conductive members are disposed in the first insulation member and have portions which are exposed on the engagement projections. Second conductive members are disposed in the second insulation member in such a way as to face the first conductive members and have portions which are exposed in the engagement grooves. A first semiconductor chip is disposed within the first insulation member and is electrically connected to the first conductive members. A second semiconductor chip is disposed in the second insulation member and is electrically connected to the second conductive members.

Stack semiconductor package and method for manufacturing the same

Growing community of inventors

Suwon, South Korea

Chul Keun Yoon