Samsung Electronics Co., Ltd.

Chul-Ho Shin

Sung-Wook Hwang

Kyeong-Koo Chi

Ik-Soo Kim

Byoung-Jae Bae

Dong-Hyun Im

Sang-sup Jeong

Gyu-Hwan Oh

Doo-Hwan Park

Sung-Un Kwon

Sang-Kuk Kim

Eun-sung Kim

Sung-Lae Cho

Shi-Yong Yi

Do-Haing Lee

Jae-woo Nam

Jeong-hyeok Choi

Kyoung-Ha Eom

Dong-Seok Lee

Keun-Hee Bai

Jong-Woo Sun

Won-woo Lee

Sang-pil Sim

Jeong-gil Lee

Shin-hye Kim

Tokashiki Ken

Joo-young Yun

U In Chung

Chang-kyu Hwang

Methods of forming contact holes include forming a first guide pattern over an etching target layer. The first guide pattern has first openings each extending in a first direction and each first opening arranged in a direction perpendicular to the first direction. A first BCP structure is formed in each first opening. The first BCP structure includes first material layers in the first direction at a first pitch in each of the first openings, and second material layers filling a remaining portion of each first opening. First holes are formed by removing the first material layers. A second guide pattern is formed over the first guide pattern and the second material layers, and the above processes are performed on the second guide pattern to form second holes. Portions of the etching target layer overlapped by the first holes or the second holes are removed to form a desired pattern.

Methods of forming contact holes

A method includes forming a hydrophilic guide layer, a DBARC layer and a photoresist film. A portion of the photoresist film and DBARC layer is exposed to form exposed and unexposed portions. The unexposed photoresist film is removed to form a photoresist pattern including the exposed photoresist film portion. A neutral layer is formed on the photoresist pattern. The photoresist pattern and the DBARC layer of the exposed portion are removed to form first opening portions exposing the guide layer. A block copolymer layer includes a block copolymer having first and second polymer blocks coated on the neutral layer while filling the first opening portions. The block copolymer layer is microphase separated to form a pattern layer including first and second patterns. A pattern including one polymer block is removed to form a pattern mask. The object layer is etched to form a pattern including second opening portions.

Methods of forming a pattern

A conductive pattern on a substrate is formed. An insulating layer having an opening exposing the conductive pattern is formed. A bottom electrode is formed on the conductive pattern and a first sidewall of the opening. A spacer is formed on the bottom electrode and a second sidewall of the opening. The spacer and the bottom electrode are formed to be lower than a top surface of the insulating layer. A data storage plug is formed on the bottom electrode and the spacer. The data storage plug has a first sidewall aligned with a sidewall of the bottom electrode and a second sidewall aligned with a sidewall of the spacer. A bit line is formed on the data storage plug.

Method of forming semiconductor device having self-aligned plug

A substrate processing method may include forming a plasma; extracting ions from the plasma and accelerating the ions to have uniform or substantially uniform directivity using a grid system; irradiating the ions at a reflector, wherein the reflector includes a plurality of reflecting plates each having a metal plate and an insulating layer on the metal plate, wherein the reflecting plates are parallel or substantially parallel such that the insulating layers are exposed to the ions; reflecting the ions incident on the reflecting plates away from the insulating layers of the reflecting plates; colliding the ions reflected away from the insulating layers with the metal plates to convert the ions into neutral beams; and irradiating the neutral beams onto a substrate to process the substrate.

Substrate processing methods for reflectors

A semiconductor device is manufactured by a method including processes of trimming and molding resist patterns. A resist layer formed on a substrate is exposed and developed to form the resist patterns. The resist patterns are trimmed using a first gas plasma to change the profiles of the resist patterns. Widths of the trimmed resist patterns are increased using a second gas plasma to form processed resist patterns.

Method of manufacturing semiconductor device

In a method of forming a semiconductor cell structure, a first insulating layer may be formed on a semiconductor substrate. A connection pattern may be formed in the first insulating layer. Second and third insulating layers may be sequentially formed on the connection pattern. The third insulating layer may be etched at least twice and the second insulating layer may be etched at least once to form a through hole in the second and third insulating layers. The through hole may expose the connection pattern.

Method of forming semiconductor cell structure, method of forming semiconductor device including the semiconductor cell structure, and method of forming semiconductor module including the semiconductor device

An apparatus and/or method for controlling an ion beam may be provided, and/or a method for preparing an extraction electrode for the same may be provided. In the apparatus, a plurality of extraction electrodes may be disposed in a path of an ion beam. At least one extraction electrode may include a plurality of sub-grids.

Apparatus and method for controlling ion beam

Example embodiments of the present invention provide a reflector for generating a neutral beam and a substrate processing apparatus including the same. The reflector may include at least one reflecting plate including a reflecting layer onto which an ion beam collides and a supporting layer. The reflecting layer may reflect and convert the ion beam into a neutral beam, and the supporting layer may reduce thermal deformation of the reflecting layer.

Reflector for generating a neutral beam and substrate processing apparatus including the same

A method of manufacturing a DRAM cell includes forming an isolation layer on a given region of a substrate to define an active region having a plurality of line shaped sub-regions; forming at least a pair of cell transistors in each line shaped sub-region, each cell transistor of a pair having a common drain region and respective source regions; forming a bit line pad on each common drain region and a storage node pad on each source region; forming a bit line pad protecting layer pattern having portions parallel to the word line, that covers the bit line pad; and forming storage nodes on storage node pads. The storage nodes of the DRAM cell contact with the storage node pads and are insulated electrically from the bit line pad by the bit pad protecting layer pattern.

DRAM cell

A method of manufacturing a DRAM cell includes forming an isolation layer on a given region of a substrate to define an active region having a plurality of line shaped sub-regions; forming at least a pair of cell transistors in each line shaped sub-region, each cell transistor of a pair having a common drain region and respective source regions; forming a bit line pad on each common drain region and a storage node pad on each source region; forming a bit line pad protecting layer pattern having portions parallel to the word line, that covers the bit line pad; and forming storage nodes on storage node pads. The storage nodes of the DRAM cell contact with the storage node pads and are insulated electrically from the bit line pad by the bit line pad protecting layer pattern.

A method for making a capacitor of a semiconductor memory device capable of providing increased capacitance without degraded resolution, as well as without the removal of any interlayer insulation layers upon formation of a lower electrode for the capacitor, wherein after formation of an access transistor on a semiconductor substrate, a first interlayer insulation layer for planarization of a surface of the semiconductor substrate and a second interlayer insulation layer for formation of the capacitor lower electrode are formed. After formation of an opening for exposing a part of an impurity diffusion region of the access transistor by etching a part of the first and second interlayer insulating layers, a spacer is formed within the opening. Further, after deposition of a conductive layer for the capacitor lower electrode onto a surface of the substrate, a planarization process is carried out until a part of the upper surface of the spacer is exposed. Finally, after removal of the exposed spacer, the dielectric layer and a conductive layer for the upper electrode of the capacitor are formed in sequence. The method does not require any additional insulation layer evaporation process, since the interlayer insulation layer for formation of the reverse storage electrode could be used for formation of a gate contact of a logic region, without removal. Consequently, simplification of fabrication process for a capacitor is achieved.

Method for fabricating a capacitor in a semiconductor memory device

A method for manufacturing a double-cylindrical storage electrode of a capacitor of a semiconductor memory device, utilizes an outer etching mask for forming an outer cylinder and an inner etching mask for forming an inner cylinder. After forming a conductive structure on a semiconductor substrate, an outer etching mask for forming an outer cylinder and an inner etching mask for forming an inner cylinder are formed on the conductive structure. Then, the conductive structure is anisotropically etched using the outer and inner etching masks, thereby forming a double-cylindrical first electrode. Since a double-cylindrical storage electrode can be obtained from a single conductive layer, the influence of native oxidation circumvented. In addition, the double-cylindrical storage electrode of the capacitor according to the present invention decreases the risk of structural fragmenting because the electrode is obtained from one material layer, instead of a combination of layers as is conventionally-known. Also, the storage electrode of the present invention has no sharp edges, so that leakage current can be minimized or avoided.

Method for manufacturing a multiple walled capacitor of a semiconductor

A method for manufacturing highly integrated NAND and NOR logic mask read only memory (MROM) devices is disclosed. Over the top surface of a semiconductor substrate, where a first polysilicon layer is formed, a pattern of a gate electrode is formed along a word line in the order of odd numbers or even numbers. Next, an insulation layer having a thickness of a submicron range is formed over the top surface of the substrate. And then a photoresist is covered and an etch back process is performed. Thereafter, the exposed insulation layer caused by the etch back process and the polysilicon layer are selectively etched to form a word line spacing corresponding to a thickness of the insulation layer. Thus, spacing between adjacent word lines can be minimized and a process margin can be sufficiently ensured.

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Yongin-si, South Korea

Chul-Ho Shin