Samsung Electronics Co., Ltd.

Chul-Ho Choi

Min-Sung Kim

Junho Song

Chang-ho An

Mi-Ran Kim

A display driver circuit including a gate driver driving gate lines of a display panel according to a driving order. The gate lines are disposed in an ordered arrangement within the display panel. A source driver converts image data corresponding to a selected gate line into an image signal and outputs the image signal to a source line of the display panel. A timing controller calculates comparison values by comparing a first image data portion corresponding to a first gate line with image data portions respectively corresponding to gate lines of the plurality of gate lines. The timing controller sets the driving order for the gate lines in response to the comparison values.

Gate driver, display driver circuit, and display device including same

A buffer amplifier includes an input stage and an output stage. The input stage has input high and low power voltages applied thereon for generating at least one transmission signal from an input signal. The output stage has output high and low power voltages applied thereon for generating an output signal from the at least one transmission signal. A first difference between the output high and low power voltages is less than a second difference between the input high and low power voltages for reducing the dynamic power consumption of the output stage.

Buffer amplifier with minimized power consumption and display driver including the same

An apparatus for transmitting data signals includes a logic unit configured to generate an encoded clock signal in response to a clock signal and a first data signal, and a demultiplexer configured to receive the encoded signal, the first data signal, and a second data signal, and to output odd-numbered data signals of the received signals at a first edge of the clock signal and even-numbered data signals of the received signals at a second edge of the clock signal. A data state elimination block is configured to receive the signals and to invert one of the received signals if logic levels of the signals are the same. An apparatus for receiving data signals according to some embodiments of the invention includes a plurality of termination resistors connected between a corresponding pad and a power source, a plurality of differential amplifiers configured to amplify a voltage difference between corresponding pads, and a logic unit configured to restore a clock signal from signals received from two of the differential amplifiers.

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Seoul, South Korea

Chul-Ho Choi