Korea Advanced Institute of Science and Technology

Other

Chul Hi Han

Choong Ki Kim

Ho Jun Lee

Jun Bo Yoon

Jae Duk Lee

Doo Won Seo

Ki Ho Han

Jae Kwan Kim

Hi Deok Lee

Eui Sik Yoon

Choon Sup Lee

A method of fabricating a refractive silicon microlens by using micro-machining technology. The method of fabricating a refractive silicon microlens according to the present invention comprises the steps of forming a boron-doped region on a silicon substrate, and selectively removing regions of the substrate except for the boron-doped region to form a lens comprised of only the boron-doped region. With the method of the present invention, it is possible to fabricate a two-dimensional infrared silicon microlens array. By using such a two-dimensional infrared silicon microlens array in an infrared sensor, the detectivity of the infrared sensor can be increased by 3.4 times, which is the refraction index of silicon. In addition, the two-dimensional infrared silicon microlens array of the present invention can be used with commercial infrared telecommunication devices.

Method of fabricating a refractive silicon microlens

A method for manufacturing a semiconductor device where a passive element, such as, an inductor, is floating over a substrate, where an integrated circuit is formed, such that the overall area of the semiconductor device may be highly reduced. According to the present invention, a first metal layer is formed on the substrate, a first masking layer is formed on a portion of the first metal layer, a second metal layer is formed on other portion of the first metal layer on which the first masking layer is not formed, and a second masking layer is formed on the first masking layer and the second metal layer. Then, the first masking layer and a portion of the second masking layer which includes a portion which covers the first masking layer is removed, a third metal layer is formed on portions of the first and second metal layers which are exposed by the step of removing the first masking layer and the portion of the second masking layer. Finally, the second masking layer, the second metal layer; and the first metal layer except a portion which the third metal layer covers are removed. In this way, the area for integrating various passive elements can be saved and the overall area for the semiconductor device including the integrated circuit and the passive elements may be reduced.

Method for manufacturing a semiconductor device having a metal layer floating over a substrate

Disclosed is an ink jet print head and a method of producing the same, the ink jet print head including a plurality of ink ejecting orifices which are formed with a desired shape and a uniform size by only once using metal plating technique, having an excellent productivity and a low manufacturing cost. According to a first embodiment of the present invention, in the steps for forming an improved metal barrier layer, which is comprised of the conventional barrier layer and the conventional nozzle plate combined together, the metal barrier layer can be formed on a wetting layer by using electrolytic plating or electroless plating of Ni. As a result, an upper surface of a first photoresist mold is completely covered with the overflowing Ni. Further, an upper portion of a second photoresist mold is partially covered with the overplating Ni and is partially opened at a proper size and a desired shape. Thereby, an ink ejecting orifice is created at the upper portion of the second photoresist mold. Alternatively, according to a second embodiment of the present invention, by forming a third photoresist mold at a predetermined position in which the ink ejecting orifice will be formed, the overflowing Ni is formed around the third photoresist mold, and thereby the ink ejecting orifice is created. The ink ejecting orifice has a desired shape, a uniform size and a high sectional height, which are adapted to provide an optimum ejection of the ink.

Ink jet print head and a method of producing the same

A heat generating type ink-jet print head including an ink supply passage for receiving an ink from an ink container, a micro chamber for storing the ink and nozzles, all being directly formed on a substrate, and a method for fabricating the ink-jet print head using an electrolytic polishing process, and a method for fabricating the ink-jet print head. The ink-jet print head is fabricated using an electrolytic polishing process, thereby achieving an accurate and inexpensive fabrication.

Heat generating type ink-jet print head

There are disclosed methods for the prevention of misfit dislocation in a silicon wafer and the silicon wafer structure manufactured thereby. A method according to an embodiment comprises the steps of: depositing a blanket silicon oxide or silicon nitride on silicon wafer in a chemical vapor deposition process; selectively etching the silicon oxide or silicon nitride, to form a silicon oxide or silicon nitride pattern which is of close shape; and injecting the silicon wafer with impurities at a high density with the CVD silicon oxide or silicon nitride pattern serving as a mask, so as to form an impurity-blocked region is formed under the CVD silicon oxide or silicon nitride through the action of the mask. The misfit dislocation is propagated mainly from the edge of wafer and an impurity-blocked region can prevent the propagation. The propagation energy is virtually based on the tensile stress attributable to the implantation of impurity. Formation of an impurity-blocked region in the wafer barricades the propagation of misfit dislocation because the propagation energy is not supplied in this region. Thus, the area of the silicon wafer enclosed by the impurity-blocked region has no misfit dislocation. By such conception, a silicon wafer free of misfit dislocation can be manufactured. Therefore, there are improved in electrical and mechanical properties in electrical devices, X-ray masks and micromachines as well as in surface roughness.

Method for the prevention of misfit dislocation in silicon wafer and

A silicon on-insulator device wafer having a very thin monocrystalline film with uniform thickness. It is fabricated by vias technique in which a monocrystalline silicon film on an insulator is etched with a base silicon etching solution in an etch apparatus by applying a vias in such a way that the solution may serve as an anode and the substrate of SOI structure as a cathode. The presence of the insulator generates vacancies in a lower region of the monocrystalline silicon film and electrons in the substrate, so that the lower region charged with the vacancies is not removed by the base silicon etching solution, thereby leaving a highly uniform, thin monocrystalline silicon film.

Growing community of inventors

Daejeon, South Korea

Chul Hi Han