Xilinx, Inc.

Chukwuweta Chukwudebe

Nabeel Shirazi

Sridhar Krishnamurthy

Bart Reynolds

Fung Fung Lee

Cheng-I Chuang

Jeffrey Mark Arnold

Kai Zhu

Tom Shui

Stephen L Bade

Anindita Patra

Srinivas Beeravolu

Raj Kumar Nagarajan

Damon McCormick

Vasanth Asokan

Disclosed approaches for creating a circuit design involving a network-on-chip (NoC) include instantiating in a memory of a computer system logic blocks and logical NoC (LNoC) blocks. Each logic block specifies a function of the circuit design and is communicatively coupled to another logic block through an LNoC block. The LNoC blocks are aggregated into a traffic specification that specifies connections between ingress circuits and egress circuits of the NoC. The traffic specification is compiled into configuration parameters for circuits of the NoC, and the logic blocks are compiled into implementation data for the target IC by the computer processor. The target IC can then be configured with the configuration parameters and implementation data.

Preparation of circuit designs for system-on-chip devices and implementation of circuitry using instances of a logical network-on-chip

In one embodiment of the present invention, a method is provided for maintaining and storing revision history of a design. The method includes, in response to a first control input by a user, determining, by a processor, module definition parameters that have changed from a design file. The changed module definition parameters are stored in the design file. For each changed module definition parameter, revision data are appended to revision history data. The revision data indicates a revision identifier, a module definition parameter identifier, and an updated value of the changed module definition parameter.

Revision history storage and maintenance

Method and apparatus are described for generating a block diagram of an electronic circuit design. In one embodiment, each instance of a multi-master bus, a bus master of a multi-master bus, a bus slave of a multi-master bus, a memory, a co-processor and an input/output port is are identified. Instances of input/output ports are placed about a perimeter of a first area of the diagram. Each instance of a multi-master bus is placed in a bus area within the first area and each bus master is placed in a master area. The bus slaves of a bus are collected in a group, and the group is placed as a single block in a slave area within the first area. The group of bus slave slaves is aligned with a bus master. A diagrammatic representation is output consistent with the placement representations.

Generation of graphical design representation from a design specification data file

In one embodiment, a method for specifying addressability in a memory-mapped device is disclosed. A data access primitive is used to model addressablity for the memory-mapped device. Addressability comprises an address matching function, a lane matching function and one or more bus connections. A first starting address for the memory-mapped device is specified. A first set of addressing matching function, lane matching function and one or more bus connections for the memory-mapped device is generated using the data access primitive and the first starting address.

Method and apparatus for specifying addressability and bus connections in a logic design

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Milpitas, CA, United States of America

Chukwuweta Chukwudebe