Broadcom Corporation

Wolley Inc.

Sibeam, Inc.

Mediatek Corporation

Wolly Inc.

Silicon Image Gmbh

Braodcom Corporation

Chuen-Shen Bernard Shung

Jeffrey M Gilbert

Karim Nassiri-Toussi

Jianhan Liu

Yu-Ming Chang

Dennis Sungik Lee

Dmitry Cherniavsky

Michael Veng-Chong Lau

Hyung Won Kim

Tom Hsiou-Cheng Kao

Pei-Feng Adrian Wang

John Marshall

Yasantha N Rajakarunanayake

Ada Shuk Yan Poon

Keangpo Ricky Ho

Sohrab Emami-Neyestanak

YungPing Hsu

Jonathan Fuchuen Lee

George Chien

Chinh Doan

Kumar Mahesh

Stephen Pope

Tim Williams

Dengwei Fu

Robert W Brodersen

Karthik Krishnaswami

Karen Wang

Tai-Chun Kuo

Dingchung Jann

Hyungwon Kim

Zhaoqian Chen

Stephen P Pope

Karim Nassiri-Tousasi

Dmitry M Cherniavsky

A method and apparatus of wear leveling control for storage class memory are disclosed. According to the present invention, where current data to be written to a nonvolatile memory corresponds to an address cache hit is determined. If the current data to be written corresponds to an address cache hit, the current data are written to a designated location in the nonvolatile memory different from a destined location in the nonvolatile memory. If the current data to be written corresponds to an address cache miss, the current data are written to the destined location in the nonvolatile memory. In another embodiment, the wear leveling control technique also includes address rotation process to achieve long-term wear leveling as well.

Apparatus and method of wear leveling for storage class memory using address cache

A method and apparatus managing online transaction using a computer system are disclosed. According to the present invention, a target request is received by a CPU coupled to a main memory and a memory application co-processor via a memory bus. The CPU then stores the target request onto the memory application co-processor coupled to a storage class memory. The memory application co-processor then locates target contents, inside the storage class memory, where the target key-word is specified in the target request. The CPU or a coupled device then accesses the target contents associated with the target key-word inside the storage class memory directly without copying the target contents associated with the target key-word inside the storage class memory to or from the main memory.

Apparatus and method of zero-copy application co-processor with storage class memory

A method and apparatus for read wearing control for storage class memory (SCM) are disclosed. The read data control apparatus, located between a host and the SCM subsystem, comprises a read data cache, an address cache and an SCM controller. The address cache stores pointers pointing to data stored in logging area(s) located in the SCM. For a read request, the read wearing control determines whether the read request is a read data cache hit, an address cache hit or neither (i.e., read data cache miss and address cache miss). For the read data cache hit, the requested data is returned from the read data cache. For the address cache hit, the requested data is returned from the logging area(s) and the read data becomes a candidate to be placed in the read data cache. For read data cache and address cache misses, the requested data is returned from SCM.

Apparatus and method of read leveling for storage class memory

A method and apparatus of bad location management for storage class memory are disclosed. A nonvolatile memory is partitioned into a non-reserved space and a reserved space, which are divided into multiple data units. The health status of the data units in the non-reserved space are classified into multiple classes including a mostly-good class. For host data read, the data from a mostly-good data unit are read and whether the data includes a pointer is checked. If no pointer, the data read are returned as the host data. Otherwise, the data unit pointed by the pointer is read. For data write, the data from a mostly-good data unit are read. If no pointer in the read data, the host data are written into the mostly-good data unit. Otherwise, the host data are written into the data unit in the reserved space pointed by the pointer.

Apparatus and method of bad location management for storage class memory using distributed pointers

An emergency mode is provided in a portable electronic device for locating a survivor in a disaster. The device includes a wireless antenna to transmit and receive wireless signals; a memory to store one or more identifiers; a user interface to receive a command that enables the emergency mode. The device also includes one or more processors, which, in response to the command, detect via the wireless receiver a predetermined identifier that matches a stored identifier identifying a sender of the predetermined identifier as a trusted node. When the predetermined identifier and a timing measurement frame are received from the trusted node, the device sends a response to the trusted node to indicate its presence.

Portable electronic devices with an emergency mode for locating survivors in disasters

A method and apparatus of wear leveling control for storage class memory are disclosed. According to the present invention, whether current data to be written to a nonvolatile memory corresponds to a write cache hit is determined. If the current data to be written corresponds to the write cache hit, the current data are written to a write cache as well as to a designated location in the nonvolatile memory different from a destined location in the nonvolatile memory. If the current data to be written corresponds to a write cache miss, the current data are written to the destined location in the nonvolatile memory. If the current data to be written corresponds to the write cache miss and the write cache is not full, the current data is also written to the write cache. In another embodiment, the wear leveling control technique also includes address rotation process to achieve long-term wear leveling as well.

Apparatus and method of damage recovery of storage class memory using repair entry in write cache

Apparatus and method of wear leveling of storage class memory by recording input group to output group address mapping

A processing device includes a first memory interface for accessing a first memory device of a main memory. Each first memory interface is compatible with Low-Power Double-Data-Rate (LPDDR) signaling. The processing device further includes a second memory interface, which has different signaling characteristics from the first memory interface, for accessing a second memory device of the main memory. The second memory device has an access latency higher than the first memory device and lower than a secondary storage device. The first memory device and the second memory device may be used as a dual memory or a two-tiered memory.

Processor memory architecture

Apparatus and method of wear leveling for storage class memory using cache filtering

A media access controller (MAC) generates a composite packet having an optimized format for carrying audio, video, and data traffic. A header portion of the composite packet is encoded separately from a data portion of the composite packet. A physical device interface (PHY) is coupled to the MAC. The PHY encodes and decodes between a digital signal and a modulated analog signal. The PHY comprises a high rate physical layer circuit (HRP) and a low rate physical layer circuit (LRP). A radio frequency (RF) transmitter is coupled to the PHY to transmit data.

Wireless HD MAC frame format

A radio frequency (RF) transmitter is coupled to and controlled by a processor to transmit data. A physical layer circuit is coupled to the RF transmitter to encode and decode between a digital signal and a modulated analog signal. The physical layer circuit comprises a high rate physical layer circuit (HRP) and a low rate physical layer circuit (LRP). The low rate channels generated by the low rate physical layer circuit (LRP) share a same frequency band as a corresponding high rate channel generated by the high rate physical layer circuit (HRP).

HD physical layer of a wireless communication device

A method and apparatus for adaptive beam-steering are disclosed. In one embodiment, the method comprises performing adaptive beam steering using multiple transmit and receive antennas, including iteratively performing a pair of training sequences, wherein the pair of training sequences includes estimating a transmitter antenna-array weight vector and a receiver antenna-array weight vector.

Adaptive beam-steering methods to maximize wireless link budget and reduce delay-spread using multiple transmit and receive antennas

A method and apparatus is disclosed herein for wireless communication with adaptive beamforming. In one embodiment, the apparatus comprises a processor, a radio frequency (RF) transmitter having a digitally controlled phased array antenna coupled to and controlled by the processor to transmit content using adaptive beamforming, and an interface to a wireless communication channel coupled to the processor to communicate antenna information relating to the use of the phased array antenna and to communicate information to facilitate playing the content at another location.

Wireless communication device using adaptive beamforming

A shared buffer packet switching device is provided for receiving data packets via associated ones of a plurality of receive ports, and for transmitting data packets via associated selected ones of a plurality of transmit port. The device includes: a shared buffer unit for temporarily storing at least a portion of each of a plurality of the data packets received via the receive ports, the shared buffer including a plurality of word locations each being associated with a shared buffer memory address value, and having an associated word storage space, the word storage spaces defining a shared buffer memory width; a tail buffer for temporarily storing remainder portions of selected ones of the received data packets, the tail buffer including a plurality of tail buffer locations each being associated with a tail buffer memory address value, and an associated tail data storage space, the tail data storage spaces defining a tail buffer memory width; and a source managing unit for receiving packets via the input ports, and being operative to store each of the received packets in selected ones of the word locations and the tail buffer locations.

Method and apparatus for shared buffer packet switching

Growing community of inventors

San Jose, CA, United States of America

Chuen-Shen Bernard Shung