Intel Corporation

Freescale Semiconductor,inc.

Fujitsu Semiconductor Limited

Apple Inc.

Freescale Semiconductors Inc.

Chuanzhao Yu

David A Newman

Hyun Yoon

Chintan S Thakkar

Kaushik Dasgupta

Anandaroop Chakrabarti

Stefan Shopov

Saeid Daneshgar

Xi Li

Stephan Leuschner

Mark Alan Kirschenmann

Qiang Li

Jorge Ivonnet

Kurt Hausmann

LiChung Chang

Salem Eid

Omid Oliaei

Luis Briones

Maximilian Eschbaumer

Michael L Gomez

Haolu Xie

Kai Zhong

Muhammed Elgousi

Stephen Rector

Dave Newman

David Newman

Amplifier circuits, radio communication circuits, radio communication devices, and methods provided in this disclosure. The amplifier circuit may include an amplifier configured to amplify an input signal to provide an output signal. The output signal of the amplifier may include a direct current (DC) signal. The amplifier circuit may further include a current source coupled to the amplifier. The current source may be configured to receive an electrical supply. The current source may further be configured to divide the direct current (DC) signal of the output signal based on the electrical supply.

Amplifier circuit with a current source

A method for harmonic trapping in a matching network of a power amplifier includes determining primary inductance and secondary inductance of a differential transformer of the matching network, based on a signal operating frequency of the power amplifier. An inductance value for an L-C filter is determined based on the secondary inductance and a harmonic frequency of a local oscillator (LO) signal. A capacitance value for the L-C filter is determined based on the inductance value and the harmonic frequency of the LO signal. The L-C filter is provided on an electric connection between a direct current (DC) bias voltage source and a secondary inductor of the differential transformer. The L-C filter is configured with the determined inductance value and the determined capacitance value.

Harmonic trapping techniques for transmitter interstage matching

Amplifier circuits, radio communication circuits, radio communication devices, and methods provided in this disclosure provide an amplifier circuit. The amplifier circuit may include an amplifier configured to amplify an input signal to provide an output signal. The amplifier circuit may further include an amplifier stack including a first transistor coupled to the amplifier. The amplifier stack may be configured to receive the output signal to amplify the output signal. The amplifier stack may be configured to receive an input control signal to control the first transistor based on an envelope of the input signal.

Amplifier circuit with an envelope enhancement

An on-chip transformer circuit is disclosed. The on-chip transformer circuit comprises a primary winding circuit comprising at least one turn of a primary conductive winding arranged as a first N-sided polygon in a first dielectric layer of a substrate; and a secondary winding circuit comprising at least one turn of a secondary conductive winding arranged as a second N-sided polygon in a second, different, dielectric layer of the substrate. In some embodiments, the primary winding circuit and the secondary winding circuit are arranged to overlap one another at predetermined locations along the primary conductive winding and the secondary conductive winding, wherein the predetermined locations comprise a number of locations less than all locations along the primary conductive winding and the secondary conductive winding.

Millimeter wave transmitter design

An inductance apparatus includes a first winding comprising a first wire section and a second wire section. The first wire section and the second wire section are disposed in a first horizontal plane associated with a center axis, and the first winding is associated with an equivalent current flow path within the first horizontal plane; a second winding extends via the center axis in the first horizontal plane to the first wire section and the second wire section, wherein the equivalent current flow path of the first winding is aligned with a current flow path associated with the second winding.

Chip multi-layer transformer and inductor

A stacked transformer or inductor apparatus including a first layer with a first layer wire element extending around a center axis and a second layer with a second layer wire element. The second layer element includes side by side first and second wire components in parallel spaced relation extending around the center axis and the first wire component is connected to the first layer wire element to form a primary turn winding. A third layer includes a third layer wire element extending around the center axis and connected to the second wire component of the second layer wire element to form a secondary turn winding partially overlapping with the primary turn winding.

On-chip multi-layer transformer and inductor

Techniques are provided for fanning out a signal from a balun. In various aspects, the system can include a balun configured to receive a signal for transmission at an input and to provide a representation of the signal at an output, a plurality of pass gate circuits, each pass gate circuit configured to receive the representation of the signal at a first node, to receive a control signal at a second node to pass the representation of the signal to a third node when the control signal is in a first state, and to isolate the representation of the signal from the third node when the control signal is in a second state. The first state of the control signal can include a non-zero voltage, and the second state of the control signal can include the non-zero voltage with a polarity opposite the non-zero voltage of the first state.

Techniques for multiple signal fan-out

Embodiments relate to a transformer-based impedance matching network that may dynamically change its characteristic impedance by engaging different inductor branches on a primary side and optionally, on the secondary side. A primary side transformer circuit includes a primary inductor () and secondary inductor () configured to provide impedance matching over a first frequency band. One or more additional inductor branches (A,B, are switchably coupled to either or both of the primary and secondary inductors to modify the impedance matching characteristics over additional operating frequencies. One or more LC filter branches () can be included at the output of the secondary side to filter harmonic frequencies in each of the operating frequency bands.

Wideband reconfigurable impedance matching network

A buffer circuit includes a first feedback buffer to receive a first component of a current-mode signal and a second feedback buffer to receive a second component of the current-mode signal. The buffer circuit also including a first inverter having a first input coupled to an output of the second feedback buffer and to an input of a first current circuit through a first filter, a first output coupled to an input of the first feedback buffer. The buffer circuit also includes a second inverter having a second input coupled to an output of the first feedback buffer and to an input of a second current circuit through a second filter, and a second output coupled to an input of the second feedback buffer.

Transceiver baseband processing

Wideband signal buffers that can be employed for mmWave (millimeter wave) communication are disclosed. One example signal buffer comprises a variable gain amplifier (VGA) that receives two control words and outputs a feedback signal, wherein both an amplitude and a phase of the feedback signal are based on the two control words and on a bias voltage; and a matching network comprising a first inductor that outputs the bias voltage, a second inductor, and a third inductor that receives the feedback signal from the VGA, and wherein the first, second, and third inductors are magnetically coupled to each other, wherein the signal buffer is configured to receive a RF (Radio Frequency) input and to generate a RF output from the RF input based on a transfer function of the signal buffer, wherein the transfer function is based at least in part on the feedback signal.

Wideband signal buffer

Apparatus and method to provide a high speed digital signal processor may implemented in a substantially all digital transmitter designs. In an embodiment, input binary bits are divided into two sets of bits, where one set is provided to a binary to thermometer coder to generate an output mixed with a clock signal to operatively provide a reverse order inverted bit pattern. The other set of binary bits is subject to exclusive-or processing such that processing of the two sets operatively provides a mixed hybrid code to be fed from high speed digital signal processor. Additional apparatus, systems, and methods are disclosed.

High-speed digital signal processing systems

A method of reducing voltage variations in a power supply may include generating an intermediate voltage and setting a first-transistor gate voltage at a first-transistor gate of a first transistor of the power supply based on the intermediate voltage. The method may also include setting an output voltage at an output node of the power supply based on a second-transistor gate voltage at a second-transistor gate of a second transistor. Additionally, the method may include setting the second-transistor gate voltage based on the first-transistor gate voltage such that the output voltage is based on the intermediate voltage, a first-transistor threshold voltage of the first transistor, and a second-transistor threshold voltage of the second transistor and such that variations in the first-transistor threshold voltage and the second-transistor threshold voltage at least partially cancel each other out.

Growing community of inventors

Phoenix, AZ, United States of America

Chuanzhao Yu