Vimicro Corporation

Chuanen Jin

Ming Wang

Xin Dong

Qingyun Cheng

Gongcheng Li

Xiaoqiang Li

Zhonghan Deng

Chunquan Dai

A direct memory access controller (DMAC) is disclosed. In one case, the DMAC is configured to manage a DMA transmission of mass data with non-continuous addresses with a nonvolatile memory. The DMAC has to transmit them in batches according to their respective continuous addresses but, different from the prior art systems, does not interrupt a CPU for each batch of the DMA transmissions. In a DMA transmission between a functional device and the nonvolatile memory, a central processor configures a link-list of cluster addresses, which is obtained from a FAT (i.e., a file allocated table) in the nonvolatile memory and may be non-continuous, in a logic address buffer. Then, a divide unit provided in the DMAC divides a non-continuous link-list of cluster addresses from the logic address buffer into a plurality of continuous sub-link-list of cluster addresses, thus the DMAC can configure each batch of DMA transmission according to the continuous sub-link-list of cluster addresses without causing impact on the CPU.

Direct memory access controller

Architectures for graphic engine chips with minimum impact on other resources are disclosed. According to one embodiment, a graphic engine architecture includes a scheduler that is configured to schedule an execution time for each of the drawing instructions sent in groups from a processor. Each drawing instruction includes a piece of time information. The scheduler is provided to fetch the drawing instructions from a FIFO buffer that buffers the drawing instructions. Subsequently, the drawing instructions are successively executed according to their scheduling.

Method and graphic engine chip for drawing processing

Techniques for multiple master devices accessing one or more slave devices via a single data bus are disclosed. According to one aspect of the techniques, a bus controller coupled between the master devices and the slave device, wherein the bus controller is configured to receive bus signals from the master devices, select one of the bus signals from one of the master devices and forwards the selected bus signal to the slave device. After the slave device receives the bus signal from the one of the master devices, the slave device sends a bus response signal to the master devices over the bus controller, and the master device from which the bus signal is selected identifies and receives the bus response signal.

Method and system for master devices accessing slave devices

Techniques for managing access to a file allocation table in an external storage device are disclosed. According to one aspect of the techniques, an accelerated apparatus, as an interface, is provided between an external storage and a device (or a host processor thereof). The accelerated apparatus comprises a center controlling unit, a FAT storage sector calculating unit, a FAT storage sector accessing unit, a buffer and a result storing unit and configured to manage the access to the FAT so that the host process is freed up to perform other tasks.

Method and apparatus for managing access to a file allocation table

Techniques for extending memory addressing with more accessing range are disclosed. According to one aspect of the techniques, an apparatus for extending addressing space comprises a plurality of extended memories, each being allocated an unique identifier, a direct addressing memory reserving a data cell as a public identifier cell for receiving the identifier of each of the extended memories to be accessed, a decision unit determining that which one of the extended memories is to be accessed by comparing an identifier received by the public identifier cell with the identifier of each of the extended memories, and a mapping unit mapping one of the extended memories determined by the decision unit to be accessed onto the direct addressing memory so that the one of the extended memories can be indirectly accessed by directly accessing the direct addressing memory.

Growing community of inventors

Beijing, China

Chuanen Jin