Sandisk 3d LLC

Intel Corporation

Sandisk Technologies Inc.

Chuanbin Pan

Chien Chiang

Yung-Tin Chen

David B Fraser

Xiying Chen

Kun Hou

Vicky M Ochoa

Andrei Mihnea

Steven Patrick Maxwell

Sychyi Fang

S Brad Herner

Tanmay Kumar

Michael L Chan

Michael Konevecki

Usha Raghuram

Huiwen Xu

Gary William Ray

Paul Wai Kie Poon

Vance Dunton

Joyce C Sum

Jeremy A Theil

Er-Xuan Ping

Qing Ma

Jian Li

Jin Hyung Lee

Abhijit Bandyopadhyay

Harry H Fujimoto

Thomas N Marieb

Ming-Che Wu

Chun Mu

Guangle Zhou

Sing-Mo Tzeng

Sing-Mo H Tzeng

Anne S Mack

John Carruthers

A resistive memory device includes a first electrode, a sidewall spacer electrode located on a sidewall of a dielectric material contacting the first electrode, a resistive memory cell containing a resistive memory material and contacting the sidewall spacer electrode, and a second electrode containing the resistive memory cell.

Resistive memory device having sidewall spacer electrode and method of making thereof

A method of making a semiconductor device includes providing an insulating layer containing a plurality of openings, forming a first semiconductor layer in the plurality of openings in the insulating layer and over the insulating layer, and removing a first portion of the first semiconductor layer, such that first conductivity type second portions of the first semiconductor layer remain in lower portions of the plurality of openings in the insulating layer, and upper portions of the plurality of openings in the insulating layer remain unfilled. The method also includes forming a second semiconductor layer in the upper portions of the plurality of openings in the insulating layer and over the insulating layer, and removing a first portion of the second semiconductor layer located over the insulating layer. The second conductivity type second portions of the second semiconductor layer remain in upper portions of the plurality of openings in the insulating layer to form a plurality of pillar shaped diodes in the plurality of openings.

Pillar devices and methods of making thereof

In some embodiments, a memory cell is provided that includes a metal-insulator-metal stack and a steering element coupled to the metal-insulator-metal stack. The metal-insulator-metal stack includes a first conductive layer, a reversible resistivity switching layer above the first conductive layer, and a second conductive layer above the reversible resistivity switching layer. The first conductive layer and/or the second conductive layer includes a first semiconductor material layer. The steering element includes the first semiconductor material layer. Numerous other aspects are provided.

Memory cells having storage elements that share material layers with steering elements and methods of forming the same

A memory cell is provided that includes a steering element, a metal-insulator-metal stack coupled in series with the steering element, and a conductor above the metal-insulator-metal stack. The steering element includes a diode having an n-region and a p-region. The metal-insulator-metal stack includes a reversible resistivity-switching material between a top electrode and a bottom electrode, and the top electrode includes a highly doped semiconductor material. The memory cell does not include a metal layer disposed between the metal-insulator-metal stack and the conductor. The bottom electrode includes the n-region or the p-region of the diode, and the reversible resistivity-switching material is directly adjacent the n-region or the p-region of the diode. Numerous other aspects are provided.

A non-volatile memory device includes a plurality of pillars, where each of the plurality of pillars contains a non-volatile memory cell containing a steering element and a storage element and at least one of a top corner or a bottom corner of each of the plurality of pillars is rounded. A method of making non-volatile memory device includes forming a stack of device layers, and patterning the stack to form a plurality of pillars, where each of the plurality of pillars contains a non-volatile memory cell that contains a steering element and a storage element, and where at least one of top corner or bottom corner of each of the plurality of pillars is rounded.

Electrode diffusions in two-terminal non-volatile memory devices

A nonvolatile memory cell including a storage element in series with a diode steering element. At least one interface of the diode steering element is passivated.

In-situ passivation methods to improve performance of polysilicon diode

In some embodiments, a memory cell is provided that includes a storage element formed from an MIM stack including (1) a first conductive layer; (2) an RRS layer formed above the first conductive layer; and (3) a second conductive layer formed above the RRS layer, at least one of the first and second conductive layers comprising a first semiconductor material layer. The memory cell includes a steering element coupled to the storage element, the steering element formed from the first semiconductor material layer of the MIM stack and one or more additional material layers. Numerous other aspects are provided.

Method of making a two-terminal non-volatile memory pillar device with rounded corner

A method of making a non-volatile memory device includes forming a first electrode, forming a steering element, forming at least one feature, forming a carbon resistivity switching material on at least one sidewall of the at least one feature such that the carbon resistivity switching material electrically contacts the steering element, and forming a second electrode.

Multilevel nonvolatile memory device containing a carbon storage material and methods of making and using same

The present invention relates to semiconductor devices. More specifically, the invention discloses the use of dummy structures to improve thermal conductivity, reduce dishing and strengthen layers formed with low dielectric constant materials.

Fabricating low K dielectric interconnect systems by using dummy structures to enhance process

A chip-on-flex package which includes at least one moisture barrier layer to prevent metal corrosion and delamination of flex component layers. An exemplary microelectronic package includes a microelectronic die having an active surface and at least one side, wherein the microelectronic die active surface includes at least one contact. A flex component is attached by a first surface to the microelectronic die active surface. At least one conductive trace is disposed on a second surface of the flex component and extends through the flex component to contact at least one of the contacts. An encapsulation material is adjacent the microelectronic die side and a bottom surface of the flex component. A moisture barrier is disposed on the flex component and the conductive trace(s). A second moisture barrier may be disposed on the encapsulation material. A heat dissipation device may also be incorporated into the chip-on-flex package.

Structures and processes for fabricating moisture resistant chip-on-flex

An integrated circuit and method for making it is described. The integrated circuit includes an insulating layer, formed within a trench that separates conductive elements of a conductive layer, that has a low dielectric constant. The insulating layer is convertible at least in part into a layer that is resistant to a plasma that may be used for a photoresist ashing step or to a solvent that may be used for a via clean step. Preferably the insulating layer comprises a silicon containing block copolymer that is convertible at least in part into a silicon dioxide layer. The silicon dioxide layer protects the remainder of the insulating layer from subsequent processing, such as photoresist ashing and via clean steps.

Silicon-rich block copolymers to achieve unbalanced vias

A process for forming air gaps in an interconnect system is disclosed. At least two conductive lines are formed upon a substrate. A low-dielectric constant material (LDCM) is formed between the at least two conductive lines. Formation of the LDCM creates first and second adhesive forces between the LDCM and the at least two conductive lines and between the LDCM and the substrate, respectively. The LDCM is expanded. A dielectric layer is formed onto the LDCM and the at least two conductive lines. Formation of the dielectric layer creates a third adhesive force between the LDCM and the dielectric layer. The LDCM is contracted. Contraction of the LDCM resulting from a fourth force within the LDCM. Each of the first, second, and third adhesive forces are substantially stronger than the fourth force.

Method for forming air gaps for advanced interconnect systems

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San Jose, CA, United States of America

Chuanbin Pan