United Microelectronics Corp.

National University of Singapore

Intel Corporation

Temasek Life Sciences Laboratory Limited

Chuan Sun

Shen-De Wang

Wang Xiang

Zhen Chen

Wei Ta

Poh Seng Lee

Weichang Liu

Wei-Chang Liu

Daniel R Lamborn

Naweed Isaak Naqvi

Nuttawut Lewpiriyawong

Kent Loong Khoo

Qi Zhou

Etch stops are disclosed for integrated circuit applications that have a set contacts of varying height, wherein there is a large height differential between the shortest and tallest contacts. In one example, an etch stop is provisioned over a 3D NAND memory staircase structure. The structure is then planarized with an insulator material that can be selectively etched with respect to the etch stop. Contact holes that land on corresponding wordlines of the staircase are etched. Due to the nature of the staircase, the holes vary in depth depending on which step of the staircase they land. The etch stop under the shallowest hole remains intact while the deepest hole is etched to completion. Once all holes have landed on the etch stop, a further etch selective to the insulator material is carried out to punch through the etch stop and expose underlying wordlines. Contacts are deposited into the holes.

Non-conductive etch stop structures for memory applications with large contact height differential

The present disclosure generally relates to a heat exchanger () and a heat exchange unit () for the heat exchanger (). The heat exchange unit () comprises: a plurality of plain fins () stacked perpendicularly to a first plane, such that a first fluid () is communicable through the first plane between the fins (); and a plurality of tubes () for communicating a second fluid () therethrough for heat exchange with the first fluid (), the tubes () extending perpendicularly through the fins (), each tube () comprising an oblique cross-section () having a pair of opposing first sides () and a pair of opposing second sides (). For each oblique cross-section (), the first sides () are perpendicular to the first plane and the second sides () are angled approximately 60&#xb0; to the first plane, the first sides () being longer than the second sides ().

Heat exchange unit and method of manufacture thereof

A multi-fluid heat exchanger () includes a primary section () and a secondary section () arranged contiguous with the primary section (). The multi-fluid heat exchanger () further includes a first heat transfer channel () arranged to carry a first fluid () and the first heat transfer channel () extends between the primary section () and the secondary section () and carries the first fluid () between the sections (). The multi-fluid heat exchanger () also includes a second heat transfer channel () disposed only at the primary section () and arranged to carry a second fluid () for heat exchange between the first and second fluids () at the primary section () and a third heat transfer channel () disposed only at the secondary section () and arranged to carry a third fluid () for heat exchange between the first and third fluids () at the secondary section ().

Multi-fluid heat exchanger

A method for forming a semiconductor device is provided, including providing a substrate having a first area comprising first semiconductor structures and a second area, wherein one of the first semiconductor structures comprises a memory gate made of a first polysilicon layer, and a second semiconductor structure comprises a second polysilicon layer disposed within the second area on the substrate; forming an organic material layer on the first semiconductor structures within the first area and on the second polysilicon layer within the second area; and patterning the organic material layer to form a patterned organic material layer, and the organic material layer exposing the memory gates of the first semiconductor structures, wherein a first pre-determined region and a second pre-determined region at the substrate are covered by the patterned organic material layer.

Method for forming a semiconductor device

A flash memory includes a substrate, a memory gate on the substrate, a charge-storage layer between the memory gate and the substrate, a select gate adjacent to the memory gate, a select gate dielectric layer between the select gate and the substrate, a first oxide-nitride spacer between the memory gate and the select gate, and a second oxide-nitride spacer. The select gate includes an upper portion and a lower portion. The second oxide-nitride spacer is disposed between the first oxide-nitride spacer and the upper portion of the select gate.

Flash memory cell

Inspecies and other plant pathogenic fungal species, the appressoriu, (infection structure) is responsible for breaching the host plant cell wall and gaining entry into the host tissues.ABC3 protein is an MDR transporter that plays an important role during host penetration and also is involved in regulating fungal response to intracellular oxidative stress. The insertional mutant abc3&#x394;, in which the ABC3 efflux pump function is blocked, lacks functional appressoria and is therefore incapable of causing disease in host plants. This invention provides the abc3 nucleic acid (gene) and ABC3 protein fromor fromorand describes methods for reducing plant pathogenicity for important rice pathogens.

Growing community of inventors

Singapore, Singapore

Chuan Sun