Massachusetts Institute of Technology

Nanyang Technological University

National University of Singapore

Chuan Seng Tan

Kwang Hong Lee

Eugene A Fitzgerald

Shuyu Bao

Eng Kian Kenneth Lee

Soo Jin Chua

Jurgen Michel

Li Hong Zhang

Yiding Lin

Kuan-Neng Chen

Wei Li

Rafael Reif

Kenneth Eng Kian Lee

Andy Fan

Gang Yih Chong

P Anantha

Keith Cheng Yeow Ng

Lin Zhang

Viet Cuong Nguyen

Ye Lin

Yew Heng Tan

Disclosed is a method of reducing surface unevenness of a semiconductor wafer (). In a preferred embodiment, the method comprises: removing a portion of a deposited layer and a protective layer thereon using a first slurry to provide an intermediate surface (). In the described embodiment, the deposited layer includes an epitaxial layer () and the protective layer includes a first dielectric layer (). The first slurry includes particles with a hardness level the same as or exceeding that of the epitaxial layer (). A slurry for use in wafer fabrication for reducing surface unevenness of a semiconductor wafer is also disclosed.

Method of reducing semiconductor substrate surface unevenness

Disclosed is a method of facilitating straining of a semiconductor element () for semiconductor fabrication. In a described embodiment, the method comprises: providing a base layer () with the semiconductor element () arranged on a first base portion () of the base layer (), the semiconductor element () being subjected to a strain relating to a characteristic of the first base portion (); and adjusting the characteristic of the first base portion () to facilitate straining of the semiconductor element ().

Method of facilitating straining of a semiconductor element for semiconductor fabrication, semiconductor platform obtained by the method, and optoelectronic device comprising the semiconductor platform

A semiconductor devicecomprising a substratehaving a through-substrate via hole, the through-substrate via holehaving formed therein: a first capacitor electrode layerand a second capacitor electrode layer, and a dielectric material layerdisposed between the first capacitor electrode layerand the second capacitor electrode layer; and a through-substrate via conductor. A method of forming a semiconductor device, the semiconductor devicecomprising a through-substrate via hole, the method comprising forming, in the through-substrate via hole: a first capacitor electrode layerand a second capacitor electrode layer, and a dielectric material layerdisposed between the first capacitor electrode layerand the second capacitor electrode layer; and a through-substrate via conductor

Semiconductor device with a through-substrate via hole having therein a capacitor and a through-substrate via conductor

A method of fabricating a device on a carrier substrate, and a device on a carrier substrate. The method comprises providing a first substrate; forming one or more device layers on the first substrate; bonding a second substrate to the device layers on a side thereof opposite to the first substrate; and removing the first substrate.

Fabrication of a device on a carrier substrate

Various embodiments may provide an optical structure. The optical structure may include a substrate. The optical structure may also include a core layer configured to carry optical light. The core layer may include germanium. The optical structure may further include an intermediate layer separating the substrate and the core layer so that the substrate is isolated from the core layer. The intermediate layer may include one or more materials selected from a group consisting of III-V materials, dielectric materials, and chalcogenide materials. A width of the core layer may be smaller than a width of the intermediate layer. A refractive index of the core layer may be more than 4. A refractive index of the intermediate layer may be smaller than 3.6.

Optical structure and method of forming the same

A method of encapsulating a substrate is disclosed, in which the substrate has at least the following layers: a CMOS device layer, a layer of first semiconductor material different to silicon, and a layer of second semiconductor material, the layer of first semiconductor material arranged intermediate the CMOS device layer and the layer of second semiconductor material. The method comprises: (i) circumferentially removing a portion of the substrate at the edges; and (ii) depositing a dielectric material on the substrate to replace the portion removed at step (i) for encapsulating at least the CMOS device layer and the layer of first semiconductor material. A related substrate is also disclosed.

Method of encapsulating a substrate

A method of manufacturing a substrate with reduced threading dislocation density is disclosed, which comprises: (i) at a first temperature, forming a first layer of wafer material on a semiconductor substrate, the first layer arranged to be doped with a first concentration of at least one dopant that is different to the wafer material; and (ii) at a second temperature higher than the first temperature, forming a second layer of the wafer material on the first layer to obtain the substrate, the second layer arranged to be doped with a progressively decreasing concentration of the dopant during formation, the doping configured to be decreased from the first concentration to a second concentration. The wafer material and dopant are different to silicon. A related substrate is also disclosed.

Method of manufacturing a substrate with reduced threading dislocation density

A method of manufacturing a germanium-on-insulator substrate is disclosed, comprising: (i) doping a first portion of a germanium layer with a first dopant to form a first electrode, the germanium layer arranged with a first semiconductor substrate; (ii) forming at least one layer of dielectric material adjacent to the first electrode to obtain a combined substrate; (iii) bonding a second semiconductor substrate to the layer of dielectric material and removing the first semiconductor substrate from the combined substrate to expose a second portion of the germanium layer with misfit dislocations; (iv) removing the second portion of the germanium layer to enable removal of the misfit dislocations and to expose a third portion of the germanium layer; and (v) doping the third portion of the germanium layer with a second dopant to form a second electrode. The electrodes are separated from each other by the germanium layer, and the first dopant is different to the second dopant.

Method of manufacturing a germanium-on-insulator substrate

A method of manufacturing a germanium-on-insulator substrate is disclosed. The method comprises: providing () a first semiconductor substrate, and a second semiconductor substrate formed with a germanium layer; bonding () the first semiconductor substrate to the second semiconductor substrate using at least one dielectric material to form a combined substrate, the germanium layer being arranged intermediate the first and second semiconductor substrates; removing () the second semiconductor substrate from the combined substrate to expose at least a portion of the germanium layer with misfit dislocations; and annealing () the combined substrate to enable removal of the misfit dislocations from the portion of the germanium layer.

A method of manufacturing a substrate is disclosed. The method comprises: providing a first semiconductor substrate, which includes an at least partially processed CMOS device layer and a layer of first wafer material; bonding a handle substrate to the partially processed CMOS device layer and removing the layer of first wafer material; providing a second semiconductor substrate having a layer of second wafer material which is different to silicon; bonding the first and second semiconductor substrates to form a combined substrate by bonding the layer of second wafer material to the partially processed CMOS device layer; and removing the handle substrate from the combined substrate to expose at least a portion of the partially processed CMOS device layer.

Method of manufacturing a substrate

A method of forming a multi-layer semiconductor structure includes attaching a handle-member to a top surface of a first structure using a first interface. At least one region of a bottom surface of the first structure is etched to form at least a first via-hole for exposing a portion of a first conductive member defined on the first structure. A conductive material is disposed in the first via-hole such that a first end of the conductive material is in electrical communication with the first conductive member and a second end of the conductive material is exposed at the bottom surface of the first structure. A second interface is disposed over at least the second end of the conductive material, which serves as a bonding and/or electrical interface between the first conductive member defined on the first structure and a second structure of the multi-layer semiconductor device structure.

Growing community of inventors

Singapore, Singapore

Chuan Seng Tan