Spansion Llc.

Intel Corporation

Cypress Semiconductor Corporation

Chuan Lin

Shibly S Ahmed

Dong-Hyuk Ju

Imran Khan

Jun Kang

Angela Tai Hui

Hidehiko Shiraiwa

Lei Xue

Kenichi Ohtsuka

Scott Allan Bell

Chang Wan Ha

Simon S Chan

Hsiao-Han Thio

Bradley Marc Davis

Richard M Fastow

Zengtao T Liu

Deepak Thimmegowda

Shankar Natarajan

Simon Siu-Sing Chan

Khaled Hasnat

Shafqat Ahmed

Binh N Ngo

Soo-yong Park

Chee Law

The total silicon area used by a plurality of high voltage transistors in an array of NAND cells is reduced by modifying the silicon area layout such that the size of the source and drain of each of the plurality of high voltage transistors is dependent on the maximum voltage to be applied to each of the source and drain for the respective one of the plurality of high voltage transistors.

Asymmetric junctions of high voltage transistor in NAND flash memory

A nonvolatile memory supports a standby state where the memory is ready to receive an access command to execute, and a deep power down state where the memory ignores all access commands. The memory can transition from the standby state to the deep power down state in response to a threshold amount of time in the standby state. Thus, the memory can enter the standby state after a command and then transition to the deep power down state after the threshold time.

Reducing power consumption in nonvolatile memory due to standby leakage current

A method includes varying spacing between at least one of a source region or a drain region and a well contact region to create a group of configurations. The method further includes determining an effect of latchup on each configuration.

Controlling the latchup effect

An integrated circuit comprises a first poly-silicon region including a first poly-silicon layer, a second poly-silicon layer disposed over the first poly-silicon layer, a first poly-silicon finger associated with the first poly-silicon layer, and a second poly-silicon finger associated with the second poly-silicon layer. The first poly-silicon finger and the second poly-silicon finger are oriented in a substantially orthogonal manner relative to each other. The integrated circuit comprises a second poly-silicon gate region including the first poly-silicon layer. The first polysilicon gate region and the second polysilicon gate region each have different poly-silicon gate structures.

Integrating transistors with different poly-silicon heights on the same die

A method of fabricating an integrated circuit including a first region and a second region each having different poly-silicon gate structures is provided. The method includes depositing a first poly-silicon layer over the first and the second region and depositing, within the second region, an oxide layer over the first poly-silicon layer. A second poly-silicon layer is deposited over the first poly-silicon layer and the oxide region. A portion of the second poly-silicon layer that lies over the oxide region is then stripped away.

A method and manufacture for memory device fabrication is provided. Spacer formation and junction formation is performed on both: a memory cell region in a core section of a memory device in fabrication, and a high-voltage device region in a periphery section of the memory device in fabrication. The spacer formation and junction formation on both the memory cell region and the high-voltage device region includes performing a rapid thermal anneal. After performing the spacer formation and junction formation on both the memory cell region and the high-voltage device region, spacer formation and junction formation is performed on a low-voltage device region in the periphery section.

Method and manufacture for embedded flash to achieve high quality spacers for core and high voltage devices and low temperature spacers for high performance logic devices

A memory device includes a substrate and source and drain regions formed in the substrate. The source and drain regions include both phosphorous and arsenic and the phosphorous may be implanted prior to the arsenic. The memory device also includes a first dielectric layer formed over the substrate and a charge storage element formed over the first dielectric layer. The memory device may further include a second dielectric layer formed over the charge storage element and a control gate formed over the second dielectric layer.

Junction leakage suppression in memory devices

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Cupertino, CA, United States of America

Chuan Lin