Taiwan Semiconductor Manufacturing Comp. Ltd.

Chuan-Li Chang

Wen-Ting Chu

Di-Son Kuo

Chia-Ta Hsieh

Ming-Chou Ho

Chang-Song Lin

Sheng-Wei Tsaur

Jake Yeh

Hsin-Ming Chen

Jack Yeh

Chang Song Lin

Chia-Da Hsieh

Ming-Chon Ho

Di-Son Kwo

Within both a method for fabricating a split gate field effect transistor and the split gate field effect transistor fabricated employing the method, there is employed a patterned silicon nitride barrier dielectric layer formed covering a first portion of a floating gate and a first portion of a semiconductor substrate adjacent the first portion of the floating gate. Within the first portion of the semiconductor substrate there is eventually formed a source/drain region, and more particularly a source region, when fabricating the split gate field effect transistor. The patterned silicon nitride barrier dielectric layer inhibits when fabricating the split gate field effect transistor ion implant damage of the floating gate and oxidative loss of a floating gate electrode edge.

Split gate field effect transistor (FET) device employing dielectric barrier layer and method for fabrication thereof

A modified nitride spacer and making of the same are disclosed. The modified nitride spacer is formed adjacent a high-temperature oxide (HTO) layer which in turn is formed adjacent the sidewalls of a gate electrode. It is shown that the placement of an intervening oxide layer between the sidewalls of the gate electrode and the nitride spacer, in that order only, provides a significant improvement in charge retention in floating gate memory cells. Also, forming of the spacer from pure, undoped oxide only yields the same favorable results.

Modified nitride spacer for solving charge retention issue in floating gate memory cell

A method is disclosed for forming a split-gate flash memory cell where the floating gate of the cell is self-aligned to a shallow trench isolation (STI), which in turn makes it self-aligned to source and to word line. This will advantageously affect a shrinkage in the size of the memory cell. In a first embodiment, the close self-alignment is made possible through a new use of an anti-reflective coating (ARC) in the various process steps of the making of the cell. In the second embodiment, a low-viscosity material is used in such a manner so as to enable self-alignment of the floating gate to the STI in a simple way.

Method of forming a floating gate self-aligned to STI on EEPROM

Within a method for fabricating a split gate field effect transistor (FET) within a semiconductor integrated circuit microelectronic fabrication, there is employed a sacrificial self aligned spacer layer which defines a control gate electrode channel within the split gate field effect transistor (FET). The sacrificial self aligned spacer layer is employed as part of an ion implantation mask employed for forming a source/drain region adjoining the control gate electrode channel within the split gate field effect transistor (FET). The sacrificial self aligned spacer layer is stripped from over the control gate electrode channel prior to forming over the control gate electrode channel a control gate electrode within the split gate field effect transistor.

Sacrificial self aligned spacer layer ion implant mask method for forming a split gate field effect transistor (FET) device

A method for fabricating a single polysilicon, non-volatile memory device, has been developed. The method features the use of a metal structure, comprised to contact an underlying control gate region, located in the semiconductor structure, in addition to providing the upper electrode, for a capacitor structure. The capacitor structure, in addition to the metal structure used as the upper electrode, is also comprised of an underlying capacitor dielectric layer, and an underlying polysilicon floating gate structure, used as the lower electrode of the capacitor structure. The creation of the capacitor structure results in performance increases realized via the additional control gate coupling capacitance, obtained via the novel configuration described in this invention.

Use of a metal contact structure to increase control gate coupling

A method for integrating salicide and high voltage device processes in the fabrication of high and low voltage devices on a single wafer is described. Isolation areas are formed on a semiconductor substrate surrounding and electrically isolating a low voltage device area from a high voltage device area. A gate oxide layer is grown in the device areas. A polysilicon layer is deposited overlying the gate oxide layer and isolation areas. A first photomask is formed over a portion of the high voltage device area wherein the first photomask also completely covers the low voltage device area. The polysilicon layer is etched away where it is not covered by the photomask to form a high voltage device. Ions are implanted to form lightly doped source and drain regions within the semiconductor substrate adjacent to the high voltage device wherein the first photomask protects the polysilicon layer in the low voltage device area from the ions. The first photomask is removed. A second photomask is formed over a portion of the low voltage device area where a gate electrode is to be formed wherein the second photomask also completely covers the high voltage device area. The polysilicon layer not covered by the second photomask is etched away to form the gate electrode. The second photomask is removed. The low voltage and high voltage area devices are silicided and the fabrication of the integrated circuit device is completed.

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Hsin-Chu, Taiwan

Chuan-Li Chang