Nan Ya Technology Corporation

Chuan-Jen Chang

Wen-Ming Lee

Ting-Shuo Hsu

Hao-Huan Hsu

Wen-Chang Cheng

Wei-Li Liu

A delay-locked loop circuit includes a delay line and a control unit. The delay line functions to delay an input signal to generate a first delay signal. The control unit receives the input signal, an access start signal and an access end signal, and functions to generate a control signal according to the input signal, the access start signal and the access end signal, wherein the control signal functions to control the delay line between two read operations.

Delay-locked loop, memory device, and method for operating delay-locked loop

A system includes a first circuit, a second circuit and a regulator. The first circuit is configured to operate at a first operating voltage, wherein the first operating voltage drops by a first voltage level while the first circuit operates. The second circuit is coupled with the first circuit at a tap, and configured to operate at a second operating voltage. The regulator is configured to provide a supply voltage to the first circuit and the second circuit via the tap. The regulator is also configured to raise the supply voltage in response to the first voltage level.

Electronic system for adjusting operating voltage and method of manufacturing the same

A dynamic random access memory (DRAM) includes a delay lock loop (DLL), a clock tree, an off-chip driver (OCD), a phase detector (PD) and a filter. The DLL receives a reference clock and updates a delay line, and then outputs a calibrated clock via the clock tree; the PD receives the calibrated clock via the clock tree and detects a phase difference between the calibrated clock and the reference clock; and the filter activates the DLL to update the delay line according the phase difference, wherein when a READ command is received, the filter increases the number of activations for the DLL to update the delay line, thereby shortening the access time of the DRAM.

Control circuit and control method for controlling delay lock loop in dynamic random access memory

The present disclosure provides a semiconductor device. The semiconductor device includes a difference-expanding device and a receiver. The difference-expanding device receives an input signal having voltage levels representing logical states, and converts the input signal to a processed signal by changing, based on the voltage levels, degrees in conduction of the difference-expanding device. The receiver receives the processed signal from the difference-expanding device, and determines the logical states of the input signal based on the processed signal.

Semiconductor device

A memory apparatus and a voltage control method of the memory apparatus are provided. The memory apparatus of the invention includes a synchronous circuit, a clock tree and a memory controller. The synchronous circuit receives a reference clock and generating a clock signal. The clock tree is coupled to an output end of the multiplexer and assigns the clock signal to a plurality of signal paths. The memory controller is coupled to the synchronous circuit and controls the synchronous circuit to adjust a frequency of the clock signal according to an operating mode of the memory apparatus.

Memory apparatus and voltage control method thereof

A memory apparatus and an operating method thereof are provided. The memory apparatus includes a memory, a temperature sensor and a control circuit. The temperature sensor senses a temperature of the memory and generating a temperature sensing signal. The control circuit is coupled to the memory and the temperature sensor. The control circuit performs access operation on the memory and changes a frequency of the access operation with reference of a delay curve according to the temperature sensing signal.

Memory apparatus and operating method thereof

The present disclosure provides a frequency-adjusting circuit comprising a temperature-sensing module, a computing module and a storage module. The temperature-sensing module is configured to measure temperatures of a plurality of DRAM chips. The storage module is coupled between the temperature-sensing module and the computing module, and is configured to store the temperatures of the plurality of DRAM chips. the computing module is coupled to the temperature-sensing module and is configured to compare the temperatures of the plurality of DRAM chips measured by the temperature-sensing module to determine a first temperature, to compare previous temperatures of the plurality of DRAM chips read from the storage module to determine a second temperature, and to compare the first temperature with the second temperature to determine a refresh frequency for the plurality of DRAM chips.

Frequency-adjusting circuit, electronic memory, and method for determining a refresh frequency for a plurality of dram chips

The present disclosure provides a detecting circuit. The detecting circuit includes a clock module, a clock receiver, a delay-locked loop module, a clock tree module, an off-chip driver, a pad, a phase detector, a voltage-detecting module and a control module. The clock module provides a clock signal to the clock receiver. The clock receiver sends the clock signal to the pad through the delay-locked loop module, the clock tree module and the off-chip driver. The control module is coupled to the voltage-detecting module and the delay-locked loop module. The voltage-detecting module is coupled between the control module and the clock tree module, and is configured to detect a voltage of the clock tree module and to send a voltage comparison information to the control module. The control module is configured to control a refresh frequency of the delay-locked loop module.

Detecting circuit, DRAM, and method for determining a refresh frequency for a delay-locked loop module

An operating method of a clock signal generating circuit includes the following operations: transmitting a clock signal to a clock tree circuit by a voltage detector; and adjusting a frequency of the clock signal according to a voltage of the clock tree circuit so as to maintain the voltage within a voltage range.

Clock signal generating circuit and operating method thereof

A system includes a regulator, a first circuit and a first sensing circuit. The regulator is configured to provide a supply voltage, and to raise the supply voltage based on a sensing result. The first circuit is configured to operate at a first operating voltage, which is derived from the supply voltage. The first sensing circuit, independent of the regulator, is configured to provide a first sensing result by sensing the first operating voltage provided to the first circuit, wherein the first sensing result serves as a first candidate for the sensing result, wherein the first sensing circuit in space of layout is closer than the regulator to the first circuit.

Electronic system for adjusting operating voltage

A voltage system and a method of operating a voltage system are provided. The voltage system includes an oscillator and a pump device. The oscillator is configured to provide an oscillation signal exhibiting a first frequency when a voltage level of a supply voltage is greater than a reference voltage level, and to provide the oscillation signal exhibiting a second frequency greater than the first frequency when the voltage level of the supply voltage is less than the reference voltage level. The pump device is configured to provide the supply voltage, based on a frequency of the oscillation signal provided by the oscillator, by performing a charging operation.

Voltage system and operating method thereof

A voltage system includes a switch device configured to regulate an output voltage at an output port of the voltage system; a pull-up device configured to pull up the output voltage of the voltage system while the pull-up device is activated; and a control device configured to activate the pull-up device when the output voltage is lower than a reference voltage.

Voltage system

The present invention provides a dynamic random access memory apparatus includes a first chip and a second chip. The first chip includes a plurality of memory cells and a plurality of through-silicon vias (TSVs). The plurality of memory cells are arranged in an array. First terminals of the TSVs are respectively coupled to the memory cells. The first chip and the second chip are overlapped, the second chip includes a plurality storage capacitors. Second terminals of the TSVs are respectively coupled to the storage capacitors storage capacitors.

Dynamic random access memory apparatus

A signal adjusting system includes: a signal generating device for generating a plurality of output signals according to a plurality of pre-output signals, a plurality of signal transmitting paths being coupled to the signal generating device for transmitting the plurality of output signals; and a controlling device coupled to the plurality of signal transmitting paths for receiving a first transmitted signal corresponding to a first output signal and a second transmitted signal corresponding to a second output signal, and detecting a phase different between the first transmitted signal and the second transmitted signal to generate a detected result to the signal generating device, wherein the signal generating device adjusts the phase difference between the first output signal and the second output signal according to the detected result.

Signal adjusting system and signal adjusting method

A memory and an operation method thereof are provided. The present invention divides memory banks of the memory into a plurality of memory groups, wherein each memory group has an independent driving power for providing an operating voltage to the corresponding memory bank in the memory group. The present invention specifies two tRRD times which are an inter-group interval and an intra-group interval. The intra-group interval is the minimum time interval between selecting one row of memory banks in a memory group to selecting another row in the memory banks of the same memory group and the inter-group interval is the minimum time interval between selecting one row of the memory banks in one memory group to selecting another row in a different memory group. Further, the inter-group interval is shorter than or equal to the intra-group interval.

Growing community of inventors

Hsinchu County, Taiwan

Chuan-Jen Chang