Richwave Technology Corp.

Winbond Electronics Corporation

Windbond Electronics Corp.

Chuan-Jane Chao

Shyh-Chyi Wong

Chi-Hung Kao

Chih-Mu Huang

Chih-Wei Chen

Chih-Wei Huang

Ying-Zong Juang

Ja-Hao Chen

Chieh-Pin Chang

Yeong-Her Wang

Chih-Sheng Chen

Shi-Tron Lin

Wei-Fan Chen

Shih-Hsien Yang

Tsyr-Shyang Liou

Chia-Jen Hsu

Jung-Yu Tsai

Kai-Ye Huang

Kuo-Jui Peng

A fixed voltage generating circuit includes a current mirror, a differential pair, and a resistor coupled to the current mirror. A node of the resistor is coupled to a voltage source. The differential pair includes two resistors coupled to the voltage source to enable the differential pair outputting a stable output voltage.

Fixed voltage generating circuit

A pizeoresistive type Z-axis accelerometer is provided, including a substrate; a plurality of anchors formed over the substrate; a plurality of cantilever beams, wherein the cantilever beams include a piezoresistive material; and a proof mass, wherein the proof mass is suspended over the substrate by respectively connecting the proof mass with the anchors, and the accelerometer senses a movement of the proof mass by the piezoresistive material.

Piezoresistive type Z-axis accelerometer

A sensing apparatus includes an acceleration sensing unit, for measuring an acceleration applied to a proof mass, further including: a proof mass; a carrier signal source, for providing a carrier signal; a capacitive half-bridge, including a first and a second capacitor, wherein each capacitor is coupled to the proof mass and the carrier signal source, one with a positive electrode and the other one with a negative electrode, and the acceleration applied to the proof mass makes the carrier signal flow through the first and the second capacitor so that the first capacitor and the second capacitor respectively generates a first voltage and a second voltage variation which have opposite phases with each other; and an instrumentation amplifier, for receiving and amplifying the first voltage and the second voltage variation, whereby the magnitude and the direction of the acceleration applied to the proof mass is determined.

Sensing apparatus

A compound semiconductor device is provided, including a gallium arsenide (GaAs) substrate having a first protrusion portion and a second protrusion portion, wherein the first protrusion portion is formed over a first portion of the GaAs substrate and the second protrusion is formed over a second portion of the GaAs substrate. A first element is disposed over the first protrusion portion, and a second element is disposed over the second protrusion portion.

Compound semiconductor device and method for fabricating the same

An adaptive bias circuit which provides a more sensitive adaptive bias current with respect to power level is used for biasing an electronic circuit. The adaptive bias circuit has a first transistor coupled to a power supply, a voltage bias circuit coupled to the first transistor and the power supply biasing the first transistor, and a first power coupling module coupled to the first transistor and the electronic circuit for coupling a portion of input signal power to the first transistor. A second transistor is coupled to the first transistor and the power supply to increase the current gain of the adaptive bias circuit, and a second current coupling module is coupled to the second transistor and the electronic circuit to provide adaptive bias current to the electronic circuit.

Adaptive bias circuit and system thereof

A high-efficiency single-to-differential amplifier has a first transistor acting as a first amplification stage. A second transistor, a third transistor, a first choke, a second choke, and a first capacitor form a second single-to-differential amplification stage. The first amplification stage receives and amplifies an input signal, outputs the amplified signal to the second single-to-differential amplification stage through a coupling module, and concurrently provides DC bias current to the second single-to-differential amplification stage through a tank. The second single-to-differential amplification stage reuses DC current of the first amplification stage, amplifies the output signal of the first amplification stage, and transfers it to a differential output.

High-efficiency single to differential amplifier

An LC resonant circuit. The LC resonant circuit comprises an inductor and a conductor. The inductor is an electrode plate of a capacitor. The conductor is over, under, or on both sides of the inductor and used as the other electrode plate of the capacitor.

LC resonant circuit

Measurement method and test structures for measuring interconnect coupling capacitance in an IC chip are provided. This method employs CBCM technique. In the first step, two test structures are used to measure a target configuration in order to obtain the total capacitance C of a metal line with respect to ground including line-to-line, fringe and area components (C=2C+2C+C). In the second step, two other test structures are used to measure a dummy configuration in order to obtain the area and fringe capacitance Cof the metal line with respect to ground including fringe and area components (C=2C+C). After the two steps, the coupling capacitance Cbetween the metal line and another line can be determined according to the formula C=(C&#x2212;C)/2.

Method and test structures for measuring interconnect coupling capacitance in an IC chip

ESD protection devices and methods of forming them are provided in this invention. By employing the thin gate oxide fabricated by a dual gate oxide process and breakdown-enhanced layers, ESD protection devices with a lower trigger voltage are provided. The NMOS structure for ESD protection according to the present invention has islands, a control gate and breakdown-enhanced layers. These islands as well as the breakdown-enhanced layers overlapping the drain region of the NMOS reduce the breakdown voltage of the PN junction in the drain region, thereby reducing the ESD trigger voltage and improving the ESD protection level of the NMOS. Furthermore, the invention is applicable to general integrated-circuit processes as well as various ESD protection devices.

ESD protection devices and methods to reduce trigger voltage

The present invention discloses a simple and convenient method for fabricating a capacitor device with BiCMOS processes. An electrode of the capacitor device formed according to the present invention is an ion doping region formed in an epitaxy layer so that the thickness of the dielectric layer of the capacitor device decreased relative to a specific ion concentration. Accordingly, the capacitor device formed therein has a high capacitance and good performance.

Method for fabricating a capacitor device with BiCMOS process and the capacitor device formed thereby

A method for measuring both buried strap and deep trench leakage currents in DRAM cell capacitors. By keeping the voltages on both plates of the capacitor equal, the buried strap leakage current (IBS) may be isolated and measured. A range of voltages is applied to a terminal of an associated transistor to obtain a corresponding range of buried strap leakage currents. An unequal voltage is next applied across the capacitor, and a total leakage current is measured. By applying a known potential to a substrate of the transistor during this total leakage current measurement, the associated IBS may be determined. Next, the IBS is subtracted from the measured total leakage current to obtain the deep trench leakage current (IDT).

Testing method for buried strap and deep trench leakage current

A method is used to fully extract coupling coefficients of a flash memory cell by a GIDL manner. The flash memory cell is composed of a substrate, a drain region, source region, a control gate and a floating gate. The method keeps the source voltage Vs and the substrate voltage Vb fixed. The drain voltage Vd and the control gate voltage are varied. Then, measuring a GIDL current obtains a first coefficient ratio of the drain coupling coefficient ad to the gate coupling &agr;cg, that is, &agr;d/&agr;cg. Similarly, keeping the drain voltage Vd and the substrate voltage Vb fixed and varying the source voltage Vs and the control gate voltage Vcg, a second coefficient ratio of the source coupling coefficient &agr;s to the gate coupling coefficient &agr;cg, that is, &agr;s/&agr;cg. Similarly, keeping the drain voltage Vd and the source voltage Vs fixed and varying the control gate voltage Vcg and the substrate voltage Vb, a third coefficient ratio of the substrate coupling coefficient &agr;b to the gate coupling coefficient &agr;cg, that is, &agr;b/&agr;cg. The first coefficient ratio &agr;d/&agr;cg, the second coefficient ratio &agr;s/&agr;cg, and the third coefficient ratio &agr;b/&agr;cg incorporate a normalization equation of &agr;d&plus;&agr;s&plus;&agr;b&plus;&agr;cg&equals;1, so that all four coefficients &agr;d, &agr;s, &agr;b, and &agr;cg can be exactly solved.

Growing community of inventors

Taipei, Taiwan

Chuan-Jane Chao