Realtek Semiconductor Inc.

Realtek Semiconductor Cotporation

Chuan-Hu Lin

Chung-Yao Chang

Yi-Syun Yang

Wei-Chieh Huang

Chia-Chun Tsui

Disclosed is a symbol timing determining device including: a symbol timing detecting circuit detecting a reception signal to obtain a first symbol timing, and shifting the first symbol timing to obtain a second symbol timing; an estimation signal generating circuit processing the reception signal according to the first and the second symbol timings respectively, so as to obtain a first and a second channel estimation frequency-domain signals; a channel estimation impulse response signal generating circuit generating a first and a second channel estimation impulse response time-domain signals according to the first and the second channel estimation frequency-domain signals respectively; a power measuring circuit measuring the energy of the first and the second channel estimation impulse response time-domain signals according to a predetermined signal region respectively; and a decision circuit selecting one of the first and the second symbol timings according to a relation of the measured energy.

Symbol timing determining device and method

A receiving device comprises an iterative decoder, a first determination unit and a control unit. The iterative decoder is for receiving at least one coded signal and for performing an iterative decoding on the at least one coded signal, to generate a plurality of decoded signals, wherein the plurality of decoded signals comprise a first decoded signal from a first iteration, a second decoded signal from a second iteration and a third decoded signal from a third iteration. The first determination unit is for determining whether the plurality of decoded signals diverge, to generate a first determination result. The control unit is for generating a control signal according to at least the first determination result, wherein the control signal indicates the iterative decoder whether to stop performing the iterative decoding on the at least one coded signal.

Device and method of controlling an iterative decoder

A receiving device comprises a channel estimation unit, for generating a plurality of channel estimates according to a plurality of reference signals; an eigenvalue computation unit, coupled to the channel estimation unit, for generating at least one eigenvalue corresponding to the plurality of channel estimates according to the plurality of channel estimates; a channel compensation unit, coupled to the eigenvalue computation unit, for generating a correlation compensation value for compensating the plurality of channels according to the at least one eigenvalue; a channel capacity computation unit, coupled to the eigenvalue computation unit and the channel compensation unit, for generating a channel capacity according to the at least one eigenvalue and the correlation compensation value; and a selection unit, coupled to the channel capacity computation unit, for determining a modulation and coding scheme (MCS) according to the channel capacity.

Device and method for determining modulation and coding scheme based on channel capacity

A method of cell search for a mobile device in a wireless communication system is provided. The method comprises performing a reception timing detection procedure, to obtain at least a possible reception time for a primary synchronization signal (PSS), performing a PSS hypothesis procedure, to generate three frequency-domain PSS sequences according to three root indexes each corresponding to a physical layer identity, and performing a secondary synchronization signal (SSS) coherent detection procedure, to calculate a SSS sequence according to each of the at least a possible reception time with the three frequency-domain PSS sequences, to obtain a physical layer cell identity group corresponding to the SSS sequence.

Method of cell search

The present invention discloses an ML (Maximum Likelihood) detector comprising: a search value selecting circuit selecting a first-layer search value; and an ML detecting circuit. The ML detecting circuit executes the following steps: selecting K first-layer candidate values according to the first-layer search value, one of a reception signal and a derivative thereof, and one of a channel estimation signal and a derivative thereof; calculating K second-layer candidate values according to the K first-layer candidate values; determining whether to add P second-layer supplemental candidate value(s) and generating a decision; when the decision is affirmative, adding the P second-layer supplemental candidate values, generating P first-layer supplemental candidate values according to the P second-layer supplemental candidate values, and calculating log likelihood ratios (LLRs) according to the (K+P) first-layer and (K+P) second-layer candidate values; and when the decision is negative, calculating LLRs according to the K first-layer and K second-layer candidate values.

Maximum likelihood detector and wireless signal receiver with maximum likelihood detection function

The present invention discloses an ML (Maximum Likelihood) detector. An embodiment of the ML detector comprises a search value selecting circuit and an ML detecting circuit. The search value selecting circuit is configured to select a first-layer search value. The ML detecting circuit is configured to carry out the following steps: selecting first-layer candidate values according to the first-layer search value, one of a reception signal and a derivative thereof, and one of a channel estimation signal and a derivative thereof, and adding one or more first-layer candidate value(s), if necessary; calculating second-layer candidate values according to all the above-mentioned first-layer candidate values, and adding one or more second-layer candidate value(s) and its/their corresponding first-layer candidate value(s), if necessary; and calculating log likelihood ratios according to the whole first-layer and second-layer candidate values.

Wireless signal receiver with maximum likelihood detector

A communication receiving end for receiving an inputted signal includes a signal amplifier for adjusting the inputted signal according to a first predetermined gain or a second predetermined gain to generate a first adjusted signal; an analog-to-digital converter (ADC), coupled to the signal amplifier, for converting the first adjusted signal; and a control unit, coupled to the ADC, for determining whether the ADC is saturated or not according to an output of the ADC. The first predetermined gain is associated with a first inputted signal power processed by the communication receiving end and a quantization noise of the ADC. The second predetermined gain is associated with a second inputted signal power processed by the communication receiving end and a full scale level of the ADC. The first inputted signal power is smaller than the second inputted signal power.

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Changhua County, Taiwan

Chuan-Hu Lin