Marvell International Limited

Marvellworld Trade Ltd.

Lsi Logic Corporation

Marvell Asia Pte., Ltd.

Chuan-Cheng Cheng

Albert M Wu

Roawen Chen

Shuhua Yu

Runzi Chang

Shiann-Ming Liou

Chien-Chuan Wei

Choy Hing Li

Scott Wu

Chung Chyung Han

Sehat Sutardja

Yauh-Ching Liu

Weidan Li

Chung Chyung (Justin) Han

Bo Wang

Peter J Wright

Hong Ying

Xin Yi Zhang

Belal Helal

Sethuraman Lakshminarayanan

Himanshu Arora

Jian-Hung Lee

Chung Chyung (Jason) Han

In an embodiment, a method comprises: forming a fin feature on a portion of a surface of a substrate; forming a first region of polycrystalline silicon over a first portion of the fin feature; forming a second region of polycrystalline silicon over a second portion of the fin feature; forming a third region of polycrystalline silicon over a third portion of the fin feature, wherein the third region of polycrystalline silicon is disposed between (i) the first region and (ii) the second region; forming a first spacer region between the first region and the third region; forming a second spacer region between the second region and the third region; removing the third region and at least a portion of the fin feature formed under the third region to thereby form a gap; and disposing a second dielectric material into the gap to form an isolation component.

Isolation components for transistors formed on fin features of semiconductor substrates

Embodiments of the present disclosure provide an apparatus comprising a semiconductor substrate having a first surface, a second surface that is disposed opposite to the first surface, wherein at least a portion of the first surface is recessed to form a recessed region of the semiconductor substrate, and one or more vias formed in the recessed region of the semiconductor substrate to provide an electrical or thermal pathway between the first surface and the second surface of the semiconductor substrate, and a die coupled to the semiconductor substrate, the die being electrically coupled to the one or more vias formed in the recessed region of the semiconductor substrate. Other embodiments may be described and/or claimed.

Package assembly including a semiconductor substrate in which a first portion of a surface of the semiconductor substrate is recessed relative to a second portion of the surface of the semiconductor substrate to form a recessed region in the semiconductor substrate

Embodiments include a semiconductor device comprising: a gate layer comprising (i) a first section and (ii) a second section, wherein the gate layer is non-linear such that the first section of the gate layer is offset with respect to the second section of the gate layer; and a first contact and a second contact, wherein the first section of the gate layer is at (i) a first distance from the first contact and (ii) a second distance from the second contact, wherein the first distance is different from the second distance.

Method and apparatus for mitigating effects of parasitic capacitance in semiconductor devices

Embodiments of the present disclosure provide a method, comprising providing a semiconductor substrate having (i) a first surface and (ii) a second surface that is disposed opposite to the first surface, forming one or more vias in the first surface of the semiconductor substrate, the one or more vias initially passing through only a portion of the semiconductor substrate without reaching the second surface, forming a dielectric film on the first surface of the semiconductor substrate, forming a redistribution layer on the dielectric film, the redistribution layer being electrically coupled to the one or more vias, coupling one or more dies to the redistribution layer, forming a molding compound to encapsulate at least a portion of the one or more dies, and recessing the second surface of the semiconductor substrate to expose the one or more vias. Other embodiments may be described and/or claimed.

Recessed semiconductor substrates and associated techniques

Embodiments of the present disclosure provide a method that includes providing a semiconductor substrate comprising a semiconductor material, forming a dielectric layer on the semiconductor substrate, forming an interconnect layer on the dielectric layer, attaching a semiconductor die to the semiconductor substrate, and electrically coupling an active side of the semiconductor die to the interconnect layer, the interconnect layer to route electrical signals of the semiconductor die. Other embodiments may be described and/or claimed.

Package assembly having a semiconductor substrate

An apparatus including a resistor capacitor network that includes an integrated high resistance resistor on top of a MOS capacitor. The resistor capacitor network includes a metal oxide semiconductor capacitor portion that includes a high-k gate oxide layer. The value of k is in a range of 4.0 to 100.0. The resistor capacitor network further includes a high resistance polysilicon gate layer formed over the high-k gate oxide layer. The resistance of the polysilicon gate layer is in a range of 100 to 2000 ohms per square.

RC networks that include an integrated high resistance resistor on top of a MOS capacitor

Embodiments of the present disclosure provide a chip that comprises a base metal layer formed over a first semiconductor die and a first metal layer formed over the base metal layer. The first metal layer includes a plurality of islands configured to route at least one of (i) a ground signal or (ii) a power signal in the chip. The chip further comprises a second metal layer formed over the first metal layer. The second metal layer includes a plurality of islands configured to route at least one of (i) the ground signal or (ii) the power signal in the chip.

Power/ground layout for chips

Some of the embodiments of the present disclosure provide a transistor comprising a p-type well; and an n-type well; wherein at least a part of one of the p-type well and the n-type well overlaps with at least a part of another of the p-type well and the n-type well. Other embodiments are also described and claimed.

Laterally diffused metal oxide semiconductor (LDMOS) device with overlapping wells

Substrates for integrated passive devices are described herein. Embodiments of the present invention provide substrates including a glass layer and at least one passive device disposed thereon. According to various embodiments of the present invention, the glass layer may have a thickness adapted to minimize conductive and/or other interactions between the substrate and the at least one passive device. Other embodiments may be described and claimed.

High resistivity substrate for integrated passive device (IPD) applications

A semiconductor wafer including an electrostatic discharge (ESD) protective device, and methods for fabricating the same. In one aspect, the method includes forming a first semiconductor device in a first semiconductor die region on the semiconductor wafer; forming a second semiconductor device in a second semiconductor die region on the semiconductor wafer; and forming a protective device in a scribe line region between (i) the first semiconductor die region and (ii) the second semiconductor die region.

Integrated circuit devices with electrostatic discharge (ESD) protection in scribe line regions

Integrated circuit devices with ESD protection in scribe line, and methods for fabricating same

A semiconductor wafer with an electrostatic discharge (ESD) protective device is disclosed. The semiconductor wafer includes first and second adjacent semiconductor die regions, a protective device in a scribe line region between the first and second die regions, and at least one metal line on a surface of the first die region, wherein the metal line(s) is/are in electrical communication with the protective device.

Growing community of inventors

Fremont, CA, United States of America

Chuan-Cheng Cheng