Excelliance Mos Corporation

Exvelliance Mos Corporation

Excellence Mos Corporation

Chu-Kuang Liu

Hung-Kun Yang

Yi-Lun Lo

A manufacturing method of a split gate trench device includes forming an epitaxial layer on a substrate, and forming a trench in the epitaxial layer, wherein the trench is divided into a first part and a second part above the first part. A shielding gate and a shielding oxide layer are then formed in the first part, wherein the shielding oxide layer is located between the shielding gate and the trench and exposes the second part. The second part is filled with an oxide, two grooves having a contour that is wide at the top and narrow at the bottom are then formed in the oxide, and a part of a sidewall of the trench is exposed. A gate oxide layer is formed on an exposed surface of the sidewall, and a first top gate and a second top gate are then formed in each of the two grooves.

Manufacturing method of split gate trench device

A trench power semiconductor device includes a substrate, an epitaxial layer, a drain, a first active device, a second active device, and isolation trench structures. The epitaxial layer and the drain are disposed on two surfaces of the substrate, respectively. The first active device is disposed in a first portion of the epitaxial layer and has a first source and a first gate. The second active device is disposed in a second portion of the epitaxial layer and has a second source and a second gate. The isolation trench structures are disposed between the first portion and the second portion of the epitaxial layer to electrically isolate the first active device and the second active device. Each of the isolation trench structures includes a polysilicon structure with a floating potential and an insulating layer. The insulating layer is between the polysilicon structure and the epitaxial layer.

Trench power semiconductor device

A trench MOSFET and a manufacturing method of the same are provided. The trench MOSFET includes a substrate, an epitaxial layer having a first conductive type, a gate in a trench in the epitaxial layer, a gate oxide layer, a source region having the first conductive type, and a body region and an anti-punch through region having a second conductive type. The anti-punch through region is located at an interface between the source region and the body region, and a doping concentration thereof is higher than that of the body region. The epitaxial layer has a first pn junction near the source region and a second pn junction near the substrate. N regions are divided into N equal portions between the two pn junctions, and N is an integer greater than 1. The closer the N regions are to the first pn junction, the greater the doping concentration thereof is.

Trench MOSFET and manufacturing method of the same

A gate structure for gallium nitride (GaN) high electron mobility transistor (HEMT) includes a heterogeneous structure, a doped GaN layer, an insulating layer, an undoped GaN layer, and a gate metal layer. The heterogeneous structure includes a channel layer and a barrier layer on the channel layer. The doped GaN layer is disposed on the barrier layer, the insulating layer is disposed on both sides of the top portion of the doped GaN layer, and the undoped GaN layer is disposed between the doped GaN layer and the insulating layer. The gate metal layer is disposed on the doped GaN layer and covers the insulating layer and the undoped GaN layer. The undoped GaN layer can protect the underlying doped GaN layer, and the insulating layer has the effect of preventing gate leakage.

Gallium nitride high electron mobility transistor and gate structure thereof

A method of manufacturing a gate structure for gallium nitride (GaN) high electron mobility transistor (HEMT) includes orderly forming a channel layer, a barrier layer, a doped GaN layer, an undoped GaN layer, and an insulating layer on a substrate, and then removing a portion of the insulating layer to form a trench. A gate metal layer is formed on the substrate to cover the insulating layer and the trench, and then a mask layer aligned with the trench is formed on the gate metal layer, wherein the mask layer partially overlaps the insulating layer. By using the mask layer as an etching mask, the exposed gate metal layer and the underlying insulating layer, the undoped GaN layer and the doped GaN layer are removed, and then the mask layer is removed.

Method of manufacturing gate structure for gallium nitride high electron mobility transistor

A power chip and a transistor structure thereof are provided. The transistor structure includes a semiconductor substrate, a plurality of gate structures, a plurality of first doped regions and a second doped region. The gate structures are disposed on the semiconductor substrate. The first doped regions are formed respectively in a plurality of first areas surrounded by the gate structures. The second doped region is formed in a second area among the gate structures. Each of the gate structures is arranged in an enclosed ring, and the shape of each of the gate structures is octagon.

Power chip and structure of transistor

A power MOSFET includes a substrate, a semiconductor layer, a first gate, a second gate, a thermal oxide layer, a first CVD oxide layer, and a gate oxide layer. The semiconductor layer is formed on the substrate and has at least one trench. The first gate is located inside the trench. The second gate is located inside the trench on the first gate, wherein the second gate has a first portion and a second portion, and the second portion is located between the semiconductor layer and the first portion. The thermal oxide layer is located between the first gate and the semiconductor layer. The first CVD oxide layer is located between the first gate and the second gate. The gate oxide layer is generally located between the second gate and the semiconductor layer.

Power MOSFET

A method of fabricating a power metal oxide semiconductor field effect transistor (MOSFET) is provided, and the method includes forming a semiconductor layer on a substrate, forming at least one first trench in the semiconductor layer, forming a thermal oxide layer on a surface of the trench, forming a first gate in the first trench, forming a chemical vapor deposition (CVD) oxide layer on the first gate in the first trench, forming a mask layer on the CVD oxide layer in the first trench so as to form a second trench between the mask layer and the thermal oxide layer, and forming a second gate in the second trench.

Method of fabricating power MOSFET

An edge terminal structure of a power semiconductor device includes a second conductive-type substrate, a first conductive-type buffer layer, a first conductive-type epitaxial layer, a first and a second electrodes, and a first and a second field plates. A trench is in a surface of the first conductive-type epitaxial layer in an edge terminal area beside an active area of the power semiconductor device. The first field plate includes at least a L-shaped electric-plate, a gate insulation layer under the L-shaped electric-plate, and the first electrode on the L-shaped electric-plate. The second field plate includes a portion of the first electrode and at least an insulation layer between the portion of the first electrode and the first conductive-type epitaxial layer. The insulation layer covers the tail of the trench and completely covers the L-shaped electric-plate.

Trench insulated gate bipolar transistor and edge terminal structure including an L-shaped electric plate capable of raising a breakdown voltage

An edge terminal structure of a trench power semiconductor device includes a first conductive-type substrate, a first conductive-type epitaxial layer thereon, a first electrode on a surface of the first conductive-type epitaxial layer, a second electrode on a back of the first conductive-type substrate, a first and a second field plates. The trench power semiconductor device includes an active area and an edge terminal area. A trench is in the surface of the first conductive-type epitaxial layer. The first field plate includes an L-shaped electric-plate, a gate insulation layer below the L-shaped electric-plate, and the first electrode on the L-shaped electric-plate. The second field plate includes a portion of the first electrode and an insulation layer between the portion of the first electrode and the first conductive-type epitaxial layer. The insulation layer covers the tail of the trench and completely covers the L-shaped electric-plate.

Trench power metal oxide semiconductor field effect transistor and edge terminal structure including an L-shaped electric plate capable of raising a breakdown voltage

An edge terminal structure of a power semiconductor device is provided that includes a substrate, a first and a second electrodes disposed on a surface and a back of the substrate respectively, a first field plate, and a second field plate. The power semiconductor device includes an active area and an edge termination area, and there is a trench in a surface of the substrate in the edge terminal area beside the active area. The first field plate is disposed on a sidewall of the trench and extends on a tail of the trench, and it includes at least a L-shaped electric-plate, a gate insulation layer under the L-shaped electric-plate, and the first electrode on the L-shaped electric-plate. The second field plate includes at least an insulation layer and the first electrode thereon. The insulation layer covers the tail of the trench and a tail of the L-shaped electric-plate further.

Power semiconductor device and edge terminal structure thereof including an L-shaped electric-plate

A power MOSFET includes an epitaxy substrate, conductive trenches, well regions and a dielectric layer. The power MOSFET further has at least one termination structure including at lest one of the conductive trenches, some of the well regions within a termination area and mutually insulated by the conductive trench, a field plate, a contact plug and a heavily-doped region. The field plate including a plate metal and the dielectric layer is on the well regions and the conductive trench within the termination area. The contact plug penetrates through the dielectric layer and connects the plate metal and one of the well regions, so the plate metal has equal potential with the connected well region through the contact plug. The well regions and the conductive trench are electrically coupled to the plate metal by the dielectric layer. The heavily-doped region is between the contact plug and the connected well region.

A method of forming a semiconductor structure is provided. A second area is between first and third areas. An epitaxial layer is formed on a substrate. A first gate is formed in the epitaxial layer and partially in first and second areas. A second gate is formed in the epitaxial layer and partially in second and third areas. A body layer is formed in the epitaxial layer in first and second areas. A doped region is formed in the body layer in the first area. All of the doped region, the epitaxial layer and the second gate are partially removed to form a first opening in the doped region and in the body layer in the first area, and form a second opening in the epitaxial layer in the third area and in a portion of the second gate. A first metal layer is filled in first and second openings.

Method of forming semiconductor structure

A semiconductor structure is provided. A second area is disposed between first and third areas. An epitaxial layer is on a substrate. A body layer is in the epitaxial layer in first and second areas. First and second gates are in the body layer and in a portion of the epitaxial layer. The first gate is in the substrate and partially in first and second areas. The second gate is in the substrate and partially in second and third areas. A first contact plug is in a portion of the body layer in the first area. A second contact plug is at least in the epitaxial layer in the third area and contacts the epitaxial layer and the second gate. The first contact plug is electrically connected to the second contact plug. A first doped region is in the body layer between the first contact plug and the first gate.

Semiconductor structure

A semiconductor structure including a substrate, at least one power MOSFET, a floating diode or a body diode, and at least one Schottky diode is provided. The substrate has a first area, a second area and a third area. The second area is between the first area and the third area. The at least one power MOSFET is in the first area. The floating diode or the body diode is in the second area. The at least one Schottky diode is in the third area. Further, the contact plugs of the power MOSFET and the Schottky diode include tungsten and are electronically connected to each other.

Growing community of inventors

Hsinchu County, Taiwan

Chu-Kuang Liu