Phison Electronics Corporation

Chu-Cheng Liang

Wee-Kuan Gan

Khein-Seng Pua

Chee-Kong Awyong

A method of reducing the frequency of erasing steps of a flash memory is described. A linking method under a mother and a child block architecture for building a check area and a logic page of the child block in order to reduce the frequency of erasing steps of the flash memory so that the service life of the flash memory can be extended and also the processing speed can be promoted.

Linking method under mother and child block architecture for building check area and logic page of the child block

A method of writing data to a large block of a flash memory cell is disclosed. When the processor writes data to the flash memory cell, if the changed data can not fill up the whole page, the processor will pick a block from one of the backed up blocks in the flash memory cell using as a special block for storing changed data temporarily, and continue to write the next changed data into the special block until whole space in the page is filled up. When the page is completely filled, then the data stored temporarily in the special block is moved to a buffer of the backed up block and then the special block is erased so that it can be used as a back up block, thus when writing data to flash memory cell, even when the change of data is unable fully fill up the whole page, the changed data still can be written continuously, and therefore the writing speed can be substantially increased.

Growing community of inventors

Hsinchu Hsien, Taiwan

Chu-Cheng Liang