Taiwan Semiconductor Manufacturing Comp. Ltd.

Tsinghua University

Chrong Jung Lin

Di-Son Kuo

Jong Chen

Shui-Hung Chen

Ya-Chin King

Hung-Der Su

Yu-Der Chih

Chia-Ta Hsieh

Jonathan Tsung-Yung Chang

Yun-Sheng Chen

Burn Jeng Lin

Jiaw-Ren Shih

Hsin-Yuan Yu

Wen Zhang Lin

Wen-Ting Chu

Maybe Chen

Shi-Jiun Wang

Jian-Hsing Lee

Yue-Der Chih

Hsin-Ming Chen

Yai-Fen Lin

Jack Yeh

May-Be Chen

Hsin Ming Chen

Chung-Li Chang

Chieh Lee

Hung Der Su

Wang-Yi Lee

Sheng-Wei Tsao

Bo Yu Lin

Shui-Hung Shen

Wen Ting Chu

Li-Yu Wang

Disclosed herein are related to a memory cell including one or more programmable resistors and a control transistor. In one aspect, a programmable resistor includes a gate structure and one or more source/drain structures for forming a transistor. A resistance of the programmable resistor may be set by applying a voltage to the gate structure, while the control transistor is enabled. Data stored by the programmable resistor can be read by sensing current through the programmable resistor, while the control transistor is disabled. In one aspect, the one or more programmable resistors and the control transistor are implemented by same type of components, allowing the memory cell to be formed in a compact manner through a simplified the fabrication process.

Memory cell including programmable resistors with transistor components

A semiconductor fabrication apparatus and a method of using the same are disclosed. In one aspect, the apparatus includes a holder configured to place a substrate and a radiation source configured to provide radiation to transfer a pattern onto the substrate. The apparatus also includes a plurality of sensing devices configured to provide a reference signal based on an intensity of the radiation when the substrate is not present. The apparatus further includes a controller, operatively coupled to the plurality of sensing devices, configured to adjust the intensity of the radiation based on the reference signal.

Semiconductor fabrication apparatus and method of using the same

A memory device includes a memory array comprising a plurality of one-time-programmable (OTP) memory cells. Each of the plurality of OTP memory cells comprises a select transistor, a diode, and a conductor fuse. The diode and the conductor fuse are coupled in series, with the select transistor coupled to a common node between the diode and the conductor fuse.

One-time-programmable memory devices

A memory device includes a first active area, a first doped structure of a first doping type, a second active area, a first gate structure and a second doped structure of a second doping type different from the first doping type. The second active area is disposed between the first active area and the first doped structure. The first gate structure is disposed between the first active area and the second active area in a layout view, and configured to store a first bit with the first active area and the second active area. The second doped structure is coupled to the first gate structure and disposed between the first doped structure and the second active area. The second doped structure and the first doped structure are configured to receive a first signal corresponding to the first bit from the first gate structure.

Memory device and system

A device includes a detector, a sensing pad, a ring structure, a control circuit, a first transistor, and a second transistor. The sensing pad is electrically connected to the detector. The ring structure is over the sensing pad and includes an upper conductive ring and a lower conductive ring between the upper conductive ring and the sensing pad. The first transistor interconnects the upper conductive ring and the control circuit. The second transistor interconnects the lower conductive ring and the control circuit.

Semiconductor device, manufacturing method thereof, and detecting method using the same

A device includes an active region, an isolation structure, a gate structure, an interlayer dielectric (ILD) layer, a reading contact, and a sensing contact. The isolation structure laterally surrounds the active region. The gate structure is across the active region. The ILD layer laterally surrounds the gate structure. The reading contact is in contact with the isolation structure and is separated from the gate structure by a first portion of the ILD layer. The sensing contact is in contact with the isolation structure and is separated from the gate structure by a second portion of the ILD layer.

Semiconductor detector

A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes a first transistor, a first resistive random access memory (RRAM) resistor, and a second RRAM resistor. The first resistor includes a first resistive material layer, a first electrode shared by the second resistor, and a second electrode. The second resistor includes the first electrode, a second resistive material layer, and a third electrode. The first electrode is electrically coupled to the first transistor.

Semiconductor device and method of manufacturing the same

A device includes a semiconductor fin, an isolation structure, a gate structure, source/drain structures, a sensing contact, a sensing pad structure, and a reading contact. The semiconductor fin includes a channel region and source/drain regions on opposite sides of the channel region. The isolation structure laterally surrounds the semiconductor fin. The gate structure is over the channel region of the semiconductor fin. The source/drain structures are respectively over the source/drain regions of the semiconductor fin. The sensing contact is directly on the isolation structure and adjacent to the gate structure. The sensing pad structure is connected to the sensing contact. The reading contact is directly on the isolation structure and adjacent to the gate structure.

Detection using semiconductor detector

A three-dimensional integrated circuit includes a plurality of perpendicular stacked chips. Each chip of the plurality of perpendicular stacked chips includes at least one transistor, a sensing coil, and a magnetic sensor, wherein the magnetic sensor is installed above the at least one transistor and the sensing coil and the sensing coil is installed between the magnetic sensor and the at least one transistor. The chip utilizes the sensing coil to generate a magnetic field including data, and a first chip of the plurality of perpendicular stacked chips adjacent to the chip utilizes a magnetic sensor of the first chip to receive the data generated by the sensing coil of the chip through the magnetic field generated by the sensing coil of the chip.

Three-dimensional integrated circuit and method of transmitting data within a three-dimensional integrated circuit

A method of making an antifuse includes providing a substrate having a bit line diffusion region and a capacitor diffusion region. A gate dielectric layer is formed over the substrate, and a word line is formed on the gate dielectric layer. An oxide layer is formed on the capacitor diffusion region, in a separate process step from forming the gate dielectric layer. A select line contact is formed above and contacting the oxide layer to form a capacitor having the oxide layer as a capacitor dielectric layer of the capacitor. The select line contact is configured for applying a voltage to cause permanent breakdown of the oxide layer to program the antifuse.

Antifuse and method of making the antifuse

A non-volatile memory device is disclosed having a charge storage layer that incorporates a plurality of nano-crystals. A substrate having a source region and a drain region is provided. Select and control gates are formed on the substrate. The charge storage layer is provided between the control gate and the substrate. The nano-crystals in the charge storage layer have a size of about 1 nm to about 10 nm, and may be formed of Silicon or Germanium. Writing operations are accomplished via hot electron injection, FN tunneling, or source-side injection. Erase operations are accomplished using FN tunneling. The control gate is formed of a single layer of polysilicon, which reduces the total number of processing steps required to form the device, thus reducing cost.

Nano-crystal gate structure for non-volatile memory

A method is provided for forming a highly dense stacked gate flash memory cell with a structure having multi floating gates that can assume 4 states and, therefore, store 2 bits at the same time. This is accomplished by providing a semiconductor substrate having gate oxide formed thereon, and shallow trench isolation and a p-well formed therein. A layer of nitride is next formed over the substrate and an opening formed therein. Polysilicon floating gate spacers are formed in the opening. A dielectric layer is then formed over the floating gates followed by the forming of a control gate. The adjacent nitride layer is then removed leaving a multi-level structure comprising a control gate therebetween multi floating gates with the intervening dielectric layer.

Multi-level (4state/2-bit) stacked gate flash memory cell

Multi-level (4 state/2-bit) stacked gate flash memory cell

Growing community of inventors

Hsin-Tien, Taiwan

Chrong Jung Lin