Advanced Micro Devices Corporation

Spansion Llc.

Advance Micro Devices, Inc.

Advanced Micro Device, Inc.

Amd Inc.

Christy Mei-Chu Woo

Minh Van Ngo

George Jonathan Kluth

Amit P Marathe

Pin-Chin Connie Wang

Paul Raymond Besser

Steven C Avanzino

Jacques J Bertrand

Connie Pin-Chin Wang

John Espinoza Sanchez, Jr

Qi Xiang

Suzette Keefe Pangrle

James N Pan

Darrell M Erb

Robert A Huertas

Paul L King

Eric N Paton

Minh Quoc Tran

Kai Yang

Ercan Adem

Jinsong Yin

Sergey D Lopatin

Matthew S Buynoski

John A Iacoponi

Dirk Dewar Brown

Diana M Schonauer

John C Foster

John Sanchez

Young-Chang Joo

Bhanwar Singh

Takeshi Nogami

Bharath Rangarajan

Imran Hashim

Robin W Cheung

Todd P Lukanc

Shekhar Pramanick

Ning Cheng

Peter A Burke

Krishnashree Achuthan

Guarionex Morales

Joffre F Bernard

Young-chang Joo

Steve Avanzino

Huade Walter Yao

Steven Douglas Bartlett

Susan Tover

An integrated circuit contact system is provided including forming a contact plug in a dielectric and forming a first barrier layer in a trench in the dielectric and on the contact plug. Further, the system includes removing a portion of the first barrier layer from the bottom of the first barrier layer and depositing the portion of the first barrier layer on the sidewall of the first barrier layer, and forming a second barrier layer over the first barrier layer and filling a corner area of the trench.

Integrated circuit contact system

A composite &#x3b1;-Ta/graded tantalum nitride/TaN barrier layer is formed in Cu interconnects with a controlled surface roughness for improved adhesion, electromigration resistance and reliability. Embodiments include lining a damascene opening, such as a dual damascene opening in a low-k interlayer dielectric, with an initial layer of TaN, forming a graded tantalum nitride layer on the initial TaN layer and then forming an &#x3b1;-Ta layer on the graded TaN layer, the composite barrier layer having an average surface roughness (Ra) of about 25 &#x212b; to about 50 &#x212b;. Embodiments further include controlling the surface roughness of the composite barrier layer by varying the Nflow rate and/or ratio of the thickness of the combined &#x3b1;-Ta and graded tantalum nitride layers to the thickness of the initial TaN layer.

Composite barrier layers with controlled copper interface surface roughness

Electromigration and stress migration of Cu interconnects are significantly reduced by forming a composite capping layer comprising a layer of tantalum nitride on the upper surface of the inlaid Cu and a layer of &#x3b1;-Ta on the titanium nitride layer. Embodiments include forming a recess in an upper surface of an upper surface of Cu inlaid in a dielectric layer, depositing a layer of titanium nitride of a thickness of 20 &#x212b; to 100 &#x212b; and then depositing a layer of &#x3b1;-Ta at a thickness of 200 &#x212b; to 500 &#x212b;.

Composite tantalum nitride/tantalum copper capping layer

The electromigration and stress migration of Cu interconnects is significantly reduced by forming a composite capping layer comprising a layer of &#x3b2;-Ta on the upper surface of the inlaid Cu, a layer of tantalum nitride on the &#x3b2;-Ta layer and a layer of &#x3b1;-Ta on the tantalum nitride layer. Embodiments include forming a recess in an upper surface of Cu inlaid in a dielectric layer, depositing a layer of &#x3b2;-Ta at a thickness of 25 &#x212b; to 40 &#x212b;, depositing a layer of tantalum nitride at a thickness of 20 &#x212b; to 100 &#x212b; and then depositing a layer of &#x3b1;-Ta at a thickness of 200 &#x212b; to 500 &#x212b;. Embodiments further include forming an overlying dielectric layer, forming an opening therein, e.g., a via opening or a dual damascene opening, lining the opening with &#x3b1;-Ta, and filling the opening with Cu in electrical contact with the underlying inlaid Cu.

Composite tantalum capped inlaid copper with reduced electromigration and reduced stress migration

A method of determining a work function of a metal to be used as a metal gate material provides a metal-on-silicon (MS) Schottky diode on a silicon substrate. The MS Schottky diode is formed by deposition of the metal in a single step deposition through a shadow mask that is secured on the silicon substrate.

Method for determining metal work function by formation of Schottky diodes with shadow mask

Method of forming composite barrier layers with controlled copper interface surface roughness

An integrated circuit having a substrate and a semiconductor device thereon. A stop layer over the substrate has a first dielectric layer formed thereon having an opening into which a first conformal barrier is formed. A first conformal barrier liner is formed in the opening, processed, and treated to improve adhesion. Portions of the first conformal barrier liner on the sidewalls act as a barrier to diffusion of conductor core material to the first dielectric layer. A conductor material is formed in the opening over the vertical portions of the first conformal barrier liner and the first stop layer.

Conformal barrier liner in an integrated circuit interconnect

High reliable copper interconnects are formed with copper or a low resistivity copper alloy filling relatively narrow openings and partially filling relatively wider openings and a copper alloy having improved electromigration resistance selectively deposited in the relatively wider openings. The filled openings are recessed and a metal capping layer deposited followed by CMP. The metal capping layer prevents diffusion along the copper-capping layer interface while the copper alloy filling the relatively wider openings impedes electromigration along the grain boundaries.

Copper interconnects with metal capping layer and selective copper alloys

A composite &#x3b1;-Ta/ graded tantalum nitride /TaN barrier layer is formed in Cu interconnects with a structure designed for improved wafer-to-wafer uniformity, electromigration resistance and reliability, reduced contact resistance, and increased process margin. Embodiments include a dual damascene structure in a low-k interlayer dielectric comprising Cu and a composite barrier layer comprising an initial layer of TaN on the low-k material, a graded layer of tantalum nitride on the initial TaN layer and a continuous &#x3b1;-Ta layer on the graded tantalum nitride layer. Embodiments include forming the initial TaN layer at a thickness sufficient to ensure deposition of &#x3b1;-Ta, e.g., as at a thickness of bout 50 &#x212b; to about 100 &#x212b;. Embodiments include composite barrier layers having a thickness ratio of &#x3b1;-Ta and graded tantalum nitride: initial TaN of about 2.5:1 to about 3.5:1 for improved electromigration resistance and wafer-to-wafer uniformity.

Cu interconnects with composite barrier layers for wafer-to-wafer uniformity

An integrated circuit and manufacturing method therefor is provided having a semiconductor substrate with a semiconductor device. A device dielectric layer is formed on the semiconductor substrate. A first dielectric layer on the device dielectric layer has an opening formed therein including a conductor reservoir volume. A barrier layer lines the channel opening. A conductor core fills the opening over the barrier layer. A second dielectric layer is formed on the first dielectric layer and has a second channel and via opening provided therein. A barrier layer lines the second channel and via opening except over the first channel opening. A conductor core fills the second channel and via opening over the barrier layer and the first conductor core to form the second channel and via. The conductor reservoir volume provides a supply of conductor material to prevent the formation of voids in the first channel and in the via.

Method for forming conductor reservoir volume for integrated circuit interconnects

A method for forming a semiconductor structure removes the temporary gate formed on the dielectric layer to expose a recess in which oxygen-rich CVD oxide is deposited. A tantalum layer is then deposited by low-power physical vapor deposition on the CVD oxide. Annealing is then performed to create a TaOregion and a Ta region from the deposited oxide and Ta. This creates a low carbon-content TaOand a metallic Ta gate in a single process step.

One step deposition method for high-k dielectric and metal gate electrode

Micro-miniaturized semiconductor devices are fabricated with silicon-rich tantalum silicon nitride replacement metal gate electrodes. Embodiments include removing a removable gate, depositing a layer of tantalum nitride, as by PVD at a thickness of 25 &#x212b; to 75 &#x212b;, and then introducing silicon into the deposited tantalum nitride layer by thermal soaking in silane or silane plasma treatment to form a layer of silicon-rich tantalum silicon nitride. In another embodiment, the intermediate structure is subjected to thermal soaking in silane or silane plasma treatment before and after depositing the tantalum nitride layer. Embodiments further include pretreating the intermediate structure with silane prior to depositing the tantalum nitride layer, treating the deposited tantalum nitride layer with silane, and repeating these steps a number of times to form a plurality of sub-layers of silicon-rich tantalum silicon nitride.

Method of manufacturing semiconductor device comprising silicon-rich tasin metal gate electrode

Low-k ILDs are protected from degradation during damascene processing by depositing a thin, conformal silicon carbide liner with a silicon-rich surface before barrier metal layer deposition. Embodiments include forming a dual damascene opening in porous low-k dielectric layers, depositing a thin silicon carbide liner with a silicon-rich surface lining the opening, depositing a barrier metal layer, such as a Ta/TaN composite, and filling the opening with Cu.

Protection of low-k ILD during damascene processing with thin liner

Gate dielectric degradation due to plasma damage during replacement metal gate processing is cured and prevented from further plasma degradation by treatment of the gate dielectric after removing the polysilicon gate. Embodiments include low temperature vacuum annealing after metal deposition and CMP, annealing in oxygen and argon, ozone or a forming gas before metal deposition, or heat soaking in silane or disilane, before metal deposition.

Gate dielectric quality for replacement metal gate transistors

Nickel film formation is implemented by heating a deposition chamber during deposition of nickel on a substrate or between processing of two or more substrates or both. Embodiments include forming a nickel silicide on a composite having an exposed silicon surface by introducing the substrate to a PVD chamber having at least one heating element for heating the chamber and depositing a layer of nickel directly on the exposed silicon surface of the composite while concurrently heating the chamber with the heating element.

Physical vapor deposition of nickel

Growing community of inventors

Cupertino, CA, United States of America

Christy Mei-Chu Woo