Advanced Micro Devices Corporation

Globalfoundies Inc.

Christy M-c Woo

Paul Raymond Besser

Minh Van Ngo

James N Pan

Jinsong Yin

Fei Wang

Lu You

Pin-Chin Connie Wang

Richard J Huang

Sergey D Lopatin

Matthew S Buynoski

Steven C Avanzino

Hiroyuki Kinoshita

Dawn M Hopper

Amit P Marathe

Kashmir S Sahota

Richard C Blish

Ercan Adem

Christine Hau-Riege

Kok-Yong Yiang

Pin Chin Connie Wang

Axel Preusse

Jun “Charlie” Zhai

The peeling stress between a Cu line and a capping layer thereon, after via patterning, is reduced by varying the shape of the via and positioning the via to increase the space between the via and the line edge, thereby increasing electromigration lifetime. Embodiments include varying the shape of the via, as by forming an oval or rectangular shape via, such that the ratio of the minor axis of the oval to the line with or the ratio of the width of the rectangle to the line width is less than about 0.7.

Copper interconnects with improved electromigration lifetime

A method for forming a semiconductor structure having a metal gate with a controlled work function includes the step of forming a precursor having a substrate with active regions separated by a channel, a temporary gate over the channel and within a dielectric layer. The temporary gate is removed to form a recess with a bottom and sidewalls in the dielectric layer. A non-silicon containing metal layer is deposited in the recess. Silicon is incorporated into the metal layer and a metal is deposited on the metal layer. The incorporation of the silicon is achieved by silane treatments that are performed before, after or both before and after the depositing of the metal layer. The amount of silicon incorporated into the metal layer controls the work function of the metal gate that is formed.

Method of forming a metal gate structure with tuning of work function by silicon incorporation

Microminiaturized semiconductor devices are fabricated with a replacement metal gate and a high-k tantalum oxide or tantalum oxynitride gate dielectric with significantly reduced carbon. Embodiments include forming an opening in a dielectric layer by removing a removable gate, depositing a thin tantalum film, as by PVD at a thickness of 25 &#x212b; to 60 &#x212b; lining the opening, and then conducting thermal oxidation, as at a temperature of 100&#xb0; C. to 500&#xb0; C., in flowing oxygen or ozone to form a high-k tantalum oxide gate dielectric layer, or in oxygen and NO or ozone and NO ammonia to form a high-k tantalum oxynitride gate dielectric. Alternatively, oxidation can be conducted in an oxygen or ozone plasma to form the high-k tantalum oxide layer, or in a plasma containing NO and oxygen or ozone to form the high-k tantalum oxynitride gate dielectric layer.

Semiconductor device with metal gate and high-k tantalum oxide or tantalum oxynitride gate dielectric

A metal gate electrode is formed with an intrinsic electric field to modify its work function and the threshold voltage of the transistor. Embodiments include forming an opening in a dielectric layer by removing a removable gate, depositing one or more layers of tantalum nitride such that the nitrogen content increases from the bottom of the layer adjacent the gate dielectric layer upwardly. Other embodiments include forming the intrinsic electric field to control the work function by doping one or more metal layers and forming metal alloys. Embodiments further include the use of barrier layers when forming metal gate electrodes.

Engineered metal gate electrode

According to one exemplary embodiment, a method for forming a contact over a silicide layer situated in a semiconductor die comprises a step of depositing a barrier layer on sidewalls of a contact hole and on a native oxide layer situated at a bottom of the contact hole, where the sidewalls are defined by the contact hole in a dielectric layer. The step of depositing the barrier layer on the sidewalls of the contact hole and on the native oxide layer can be optimized such that the barrier layer has a greater thickness at a top of the contact hole than a thickness at the bottom of the contact hole. According to this exemplary embodiment, the method further comprises a step of removing a portion of the barrier layer and the native oxide layer situated at the bottom of the contact hole to expose the silicide layer.

Method for preventing an increase in contact hole width during contact formation

A semiconductor device includes a first metallization layer, a first diffusion barrier layer, a second etch stop layer, a first dielectric layer, a first etch stop layer, a second dielectric layer, a trench extending through the second dielectric layer and the first etch stop layer, and a via extending through the first dielectric layer, the second etch stop layer, and the first diffusion barrier layer. The first diffusion barrier layer is disposed over the first metallization layer. The second etch stop layer is disposed over and spaced from the first diffusion barrier layer, and the first dielectric layer is disposed over the second etch stop layer. The via can also have rounded corners. A third etch stop layer can also be disposed between the first diffusion barrier layer and the second etch stop layer. A sidewall diffusion barrier layer can be disposed on sidewalls of the via and trench, and the sidewall diffusion barrier layer is formed from the same material as the first diffusion barrier layer. A method of manufacturing the semiconductor device is also disclosed.

Dual damascene integration scheme for preventing copper contamination of dielectric layer

A semiconductor device includes a first metallization level, a first diffusion barrier layer, a first etch stop layer, a dielectric layer and an opening extending through the dielectric layer, the first etch stop layer, and the first diffusion barrier layer. The first diffusion barrier layer is disposed over the first metallization level. The first etch stop layer is disposed over the first diffusion barrier layer, and the dielectric layer is disposed over the first etch stop layer. The opening can also have rounded corners. A sidewall diffusion barrier layer can be disposed on sidewalls of the opening, and the sidewall diffusion barrier layer is formed from the same material as the first diffusion barrier layer. The first etch stop layer can be formed from a material different than the first barrier layer, and the material of the first barrier layer can be selected from the group consisting of tantalum, titanium, tantalum nitride, titanium nitride, and tungsten nitride. Metal within the opening form a second metal feature, and the metal can comprise copper or a copper alloy. A method of manufacturing the semiconductor device is also disclosed.

Use of ta/tan for preventing copper contamination of low-k dielectric layers

In the present method of fabricating a semiconductor device, openings of different configurations (for example, different aspect ratios) are provided in a dielectric layer. Substantially undoped copper is deposited over the dielectric layer, filling the openings and extending above the dielectric layer, the different configurations of the openings providing an upper surface of the substantially undoped copper that is generally non-planar. A portion of the substantially undoped copper is removed to provide a substantially planar upper surface thereof, and a layer of doped copper is deposited on the upper surface of the substantially undoped copper. An anneal step is undertaken to difffuse the doping element into the copper in the openings.

Integration scheme for non-feature-size dependent cu-alloy introduction

An interconnect opening of an integrated circuit is filled with a conductive fill, such as copper, with the interconnect opening being within an insulating layer on a semiconductor wafer. A seed layer of a first alloy is deposited conformally onto sidewalls and a bottom wall of the interconnect opening. The first alloy is comprised of a first metal dopant in a bulk conductive material. The first metal dopant has a relatively high solid solubility in the bulk conductive material, and the first metal dopant has a concentration in the bulk conductive material of the seed layer that is lower than the solid solubility of the first metal dopant in the bulk conductive material. At least a portion of the conductive fill grown from the seed layer is comprised of a second alloy with a second metal dopant having a relatively low solid solubility in the bulk conductive material, and the second metal dopant has a concentration in the conductive fill that is higher than the solid solubility of the second metal dopant in the bulk conductive material. A thermal anneal is performed to form an additional encapsulating material that covers a top surface of the conductive fill, and the additional encapsulating material is formed from the second metal dopant diffusing out of the conductive fill during the thermal anneal. A layer of bulk passivation material is formed over the additional encapsulating material and the insulating layer. Use of the first alloy of the seed layer prevents agglomeration of the bulk conductive material of the seed layer at the sidewalls of the interconnect opening. The additional encapsulating material prevents drift of material from the conductive fill along the bottom surface of the layer of bulk passivation material and into the surrounding insulating layer.

Filling an interconnect opening with different types of alloys to enhance interconnect reliability

In a method for filling an interconnect opening to form an interconnect of an integrated circuit, the interconnect opening is formed within an insulating layer. The interconnect opening is partially filled with a conductive material to form a recess within the conductive material toward a top of the interconnect opening, and the recess is disposed within the interconnect opening. An alloy is conformally deposited to fill the recess. Any conductive material and the alloy on the insulating layer are polished away such that the conductive material and the alloy are contained within the interconnect opening. A thermal anneal is then performed such that the conductive material and the alloy form into a conductive fill of a single grain structure within the interconnect opening. An additional encapsulating material is formed to cover a top surface of the conductive fill during the thermal anneal from the dopant of the alloy diffusing out of the alloy and along the top surface of the conductive fill. A bulk encapsulating layer is formed on top of the additional encapsulating material and on top of the insulating layer. The present invention may be used to particular advantage when the conductive material that partially fills the interconnect opening is copper, and when the alloy that fills the recess is a copper alloy with a dopant metal having a solid solubility in copper that is less than 0.1 atomic percent at room temperature and having a concentration in the copper alloy that is greater than the solid solubility in the copper alloy. In this manner, the additional encapsulating material on the top surface of the conductive fill prevents lateral drift of the conductive material comprising the conductive fill along a bottom surface of the bulk encapsulating layer.

Forming and filling a recess in interconnect with alloy to minimize electromigration

The reliability of Cu and Cu alloy interconnects is significantly enhanced by controlling the temperature of the electroplating solution during via opening filling to substantially prevent occlusion of the opening. Embodiments of the present invention include electroplating Cu or a Cu alloy from an electroplating solution at a temperature of about 20.degree. C. or less.

Method of forming reliable copper interconnects with improved hole

A chemical mechanical polisher is provided comprising multiple polish platens to sequentially remove any fixed amount of oxide or metal on a semiconductor wafer. Each polish platen polishes a fraction of the total oxide removed. Total oxide removal is achieved after completing polishing on all available polish platens assigned for polishing. Reduced oxide removed enables a high oxide removal rate on each polish platen, thus reducing polish time. Sequential polishing on multiple polish platens reduces polish time especially for high oxide removal in the range greater than 0.5 micrometer to greater than 1 micrometer. A higher polish rate and shorter polish time results in shorter polish pad conditioning time. Multiple polish platens coupled with more than one consecutive wafer-carrier head, each following the previous wafer-carrier head in completing sequential polishing, improves machine throughput by eliminating machine idle time caused by events other than actual oxide or metal polishing. The throughput can be further increased by polishing more than one wafer simultaneously at the same polish platen by: (1) employing wafer-carrier heads that hold a set of wafers, (2) providing sets of wafer-carrier heads which follow the same path simultaneously and polish simultaneously at the same polish platen or (3) employing a combination of both methods. The polishing of metals enables use of different polish pad materials and slurry chemistries for each polish platen.

Performing chemical mechanical polishing of oxides and metals using

The present invention is directed to improving the throughput of the process for fabricating multilayer interconnects. Tungsten plugs, formed in contact/via openings etched in an interlayer dielectric, have been widely used in industry to form interconnection between different metal layers. An adhesion layer comprising a Ti/TiN stack is typically employed to support the adhesion of the tungsten plug in the contact/via openings. The present invention is directed to a process involving the formation of a Ti/TiN landing pad at the base of contact/via openings prior to the deposition of the interlayer dielectric. The process of the present invention enables the removal of the Ti under-layer and the reduction of the TiN thickness in the Ti/TiN stack. The throughput of the process for fabricating multilayer interconnects is thus greatly improved while the integrity of the devices are maintained.

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San Jose, CA, United States of America

Christy M-c Woo