Texas Instruments Corporation

University of Florida Research Foundation Inc

Christy Leigh She

Steven Craig Bartling

Sudhanshu Khanna

Veeramanikandan Raju

Anand Kumar G

Michael Zwerg

Hao Meng

Jose Carlos Principe

Krishnasawamy Nagaraj

John Gregory Harris

Srinivasa Chakravarthy

Joonsung Park

Harish Maruthiyodan

Mangesh Subhash Dhantole

Methods for operating two or more analog-to-digital converters (ADCs) are presented herein. The method may be implemented in an integrated circuit. The integrated circuit may include a first ADC and a second ADC disposed on a single semiconductor die. The integrated circuit may also include logic circuitry operably coupled to the first and second ADCs. For a digital value obtained by conversion, by the first ADC, of a first analog signal sampled by the first ADC during a period of time overlapping with another period of time during which a second analog signal is being converted by the second ADC, the logic circuitry may be configured to cause the digital value to be marked as noisy.

Analog-to-digital convertors positioned on a single semiconductor die

A method for configuring a target peripheral via a hardware request is provided. The method includes receiving a hardware request from one of a plurality of initiator peripherals, receiving a configuration selection from the requesting initiator peripheral, and selecting a configuration from a plurality of hardware memory locations based at least in part on the configuration selection. The method also includes configuring one or more signal processing modules within the target peripheral based at least in part on the configuration, receiving a signal from an electronic device, and processing the signal from the electronic device with the one or more signal processing modules. The method further includes transmitting a processed signal from the signal processing modules to the requesting initiator peripheral.

Real time peripheral configuration via hardware request

A system and method for dynamically protecting against security vulnerabilities in a reconfigurable signal chain. The system includes a signal chain formed from at least a first component connected with a second component. The first component has a set of source outputs and a first authentication block, and the second signal chain component has a set of destination inputs and a second authentication block. The system also includes a signal chain configurator that populates the first authentication block with at least one validated endpoint from the set of destination inputs. A signal chain integrity block, which is communicatively coupled with the first authentication block and the second authentication block, identifies a source-destination pair from one or more endpoint pairs formed from the at least one validated endpoint and the set of source outputs. The signal chain integrity block propagates the source-destination pair to the first authentication block and the second authentication block. The second authentication block authenticates any received input using the source-destination pair.

Dynamic security protection in configurable analog signal chains

Disclosed examples include non-volatile counter systems to generate and store a counter value according to a sensor pulse signal, and power circuits to generate first and second supply voltage signals to power first and second power domain circuits using power from the sensor pulse signal, including a switch connected between first and second power domain supply nodes, a boost circuit, and a control circuit to selectively cause the switch to disconnect the first and second power domain circuits from one another after the first supply voltage signal rises above a threshold voltage in a given pulse of the sensor pulse signal, and to cause the boost circuit to boost the second supply voltage signal after the regulator output is disconnected from the second power domain supply node in the given pulse.

Non-volatile counter system, counter circuit and power management circuit with isolated dynamic boosted supply

A multi-scale spike detector for performing multi-resolution spike detections of a signal is provided. The spike detector includes a gamma filter having cascaded low-pass filters. The cascaded filters collectively provide different cutoff frequencies, each of the filters having a respective output. One of the filters has an input, at which the signal is received. The spike detector further includes combining circuitry that combines at least some of the respective outputs of the cascaded filters. The differences formed from this combining provide a waveform representation of the input signal. The waveform representation consists essentially of spikes that occur in the signal.

Low power, wavelet-based spike detector

Growing community of inventors

Allen, TX, United States of America

Christy Leigh She