Intel Corporation

Christos E Kotselidis

Raul Martinez

Fernando Latorre

Grigorios Magklis

Pedro Lopez

Marc Lupon

Pedro Marcuello

Polychronis Xekalakis

Josep M Codina

Enric Gibert Codina

Carlos Madriles

Daniel Ortega

Kyriakos A Stavrou

Demos Pavlou

Georgios Tournavitis

Mirem Hyuseinova

Crispin Gomez Requena

Antonio Gonzalez

Alejandro Martinez Vicente

Alejandro Vicente Martinez

Carlos Madriles Gimeno

Marti Torrents Lapuerta

Alejandro M Vicente

Joseph M Codina

Antonio Gonzelez

A computer-readable storage medium, method and system for optimization-level aware branch prediction is described. A gear level is assigned to a set of application instructions that have been optimized. The gear level is also stored in a register of a branch prediction unit of a processor. Branch prediction is then performed by the processor based upon the gear level.

Instruction and logic for optimization level aware branch prediction

A combination of hardware and software collect profile data for asynchronous events, at code region granularity. An exemplary embodiment is directed to collecting metrics for prefetching events, which are asynchronous in nature. Instructions that belong to a code region are identified using one of several alternative techniques, causing a profile bit to be set for the instruction, as a marker. Each line of a data block that is prefetched is similarly marked. Events corresponding to the profile data being collected and resulting from instructions within the code region are then identified. Each time that one of the different types of events is identified, a corresponding counter is incremented. Following execution of the instructions within the code region, the profile data accumulated in the counters are collected, and the counters are reset for use with a new code region.

Propagating a prefetching profile bit from a prefetch queue to a data cache to indicate that a line was prefetched in response to an instruction within a code region

Disclosed is an apparatus and method to manage instruction cache prefetching from an instruction cache. A processor may comprise: a prefetch engine; a branch prediction engine to predict the outcome of a branch; and dynamic optimizer. The dynamic optimizer may be used to control: identifying common instruction cache misses and inserting a prefetch instruction from the prefetch engine to the instruction cache.

Managed instruction cache prefetching

Techniques for implementing identification and management of unsafe optimizations are disclosed. A method of the disclosure includes receiving, by a managed runtime environment (MRE) executed by a processing device, a notice of misprediction of optimized code, the misprediction occurring during a runtime of the optimized code, determining, by the MRE, whether a local misprediction counter (LMC) associated with a code region of the optimized code causing the misprediction exceeds a local misprediction threshold (LMT) value, and when the LMC exceeds the LMT value, compiling, by the MRE, native code of the optimized code to generate a new version of the optimized code, wherein the code region in the new version of the optimized code is not optimized.

Identification and management of unsafe optimizations

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Barcelona, Spain

Christos E Kotselidis