Lexmark International, Inc.

Marvell International Limited

Christopher Wilson Case

James Ray Bailey

Michael Anthony Marra, Iii

James Alan Ward

James Patrick Sharpe

Douglas G Keithley

Keith Bryan Hardin

Zachary Nathan Fister

David Allen Crutchfield

Mark Lane Mayberry

Joseph Kamal Yackzan

Karl Mark Thompson

Brian Allen Craw

Bennett Fornal

A system including a rotate block including an array of bit storage units for storing image data bits of a subtile of an image to be rotated, the image data bits of the subtile being arranged in a plurality of subtile rows. The rotate block is operative to load the image data bits of each subtile row of the subtile into the array according to a subtile row load direction that is selected from a plurality of load directions based at least upon a rotate operation to be performed on the image. After loading all the image data bits of the subtile into the array, the rotate block repeatedly unloads image data bits out of the array to produce a rotated subtile. The image data bits that are unloaded from the array from each unloading operation form a subtile row of the rotated subtile.

System and method for performing orthogonal rotation and mirroring operation in a device

A method for reducing electromagnetic emissions by an image scanner comprises cyclically dithering a frequency of a clock signal of the image scanner by repeated dither cycles, determining a phase of the dither cycle when a scan pass of a page of a document commences; and commencing all subsequent scan passes of the page of the document at a particular phase shift from the determined phase of the dither cycle.

Method and apparatus for scanning an image

A system for testing or debugging a device under test having an embedded logic analyzer. In one embodiment, the system includes software stored in non-transitory memory for testing a device under test having an embedded logic analyzer, the software program product having instructions which, when executed by a computing device associated with the device under test cause the computing device to reconstruct signals of interest in the device under test based at least in part upon signals captured by the embedded logic analyzer during the test or debug session, and cause the computing device to display the reconstructed signals of interest to a user of the computing device.

System and method for analyzing an electronics device including a logic analyzer

A system for testing or debugging a system including the integrated circuit having an embedded logic analyzer. In one embodiment, the system includes a computing device coupled to the logic analyzer for receiving the at least one output. A user interface run on the computing device assigns an attribute to at least one signal associated with the logic analyzer, determines a new signal or value not provided by the logic analyzer, the new signal or value being based upon the at least one signal as received from the logic analyzer and upon a predetermined definition, and presents the new signal or value to a system user.

The invention describes an electronic device and a method for operating the electronic device. The electronic device includes one or more circuit components. The electronic device further includes one or more fuses and one or more non-volatile memories to disable the access of at least one of the one or more circuit components. Each of the one or more non-volatile memories includes one or more firmware, which are used to program at least one bit to manage the access of the at least one circuit component. The method includes performing a power-up sequence in a power cycle for the electronic device. The method further includes determining a state of circuit and a state of a bit for selectively enabling a test function.

Electronic device and method for operating the electronic device

An integrated circuit including a logic analyzer with enhanced analyzing and debugging capabilities and a method therefore. In one embodiment, an integrated circuit includes a logic analyzer having a first input receiving a plurality of signals and an output for providing an indication of a detection, by the logic analyzer, of at least one trigger event; and a built in self test block having a first input for receiving one or more of the signals appearing at the first input of the logic analyzer, a second input coupled to the output of the logic analyzer for selectively enabling the BIST block, the BIST block generating and maintaining a signature based upon the first and second inputs thereof.

Integrated circuit including a programmable logic analyzer with enhanced analyzing and debugging capabilities and a method therefor

A method for generating transposed image data for use in an imaging apparatus having access to a memory includes (a) generating a set of data blocks corresponding to at least a portion of image data representing an image to be printed; (b) performing a combined format and transpose operation on the set of data blocks; and (c) storing a result of the combined format and transpose operation in the memory.

Method for generating transposed image data

A method of scaling and rotating an image includes generating a scaled and rotated pixel grid from a transformation operation applied to an input pixel grid. The input pixel grid comprises a plurality of pixels representing an original image, and the transformation may implement the simultaneous scaling and rotation of the input pixel grid. The respective values of a plurality of output pixels in the scaled and rotated pixel grid are then determined by interpolation.

Growing community of inventors

Georgetown, KY, United States of America

Christopher Wilson Case