Arm Limited

Christopher William Laycock

Bruce James Mathewson

Richard Roy Grisenthwaite

Antony John Harris

Peter Andrew Riocreux

Stuart David Biles

Andrew Christopher Rose

Arthur Brian Laughton

A memory interface apparatusis provided with first interface circuitry, second interface circuitryand transaction control circuitry. The first interface circuitry receives a first write request from a transaction masterand issues a further transaction request associated with the memory address of the first write request via the second interface circuitry to a memory system. When an indication of the completion of the further transaction has been received at the second interface circuitry, then a second write request may be issued from the second interface circuitry to the memory system to write the target data associated with the first write request. After a write response signal in respect of the second write request is received at the second interface circuitry, then an acknowledge signal RACK indicating completion of the further transaction and that the write response signal has been received may be issued from the second interface circuitry. Between issue of the further transaction and issue of the acknowledge signal snoop requests to the memory addresses concerned that arise elsewhere within the memory system may be managed and blocked.

Memory interface control

Interconnect circuitry is configured to provide data routes via which at least one initiator device may access at least one recipient device. The circuitry including: at least one input for receiving transaction requests from at least one initiator device; at least one output for outputting transaction requests to the at least one recipient device; and at least one path for transmitting transaction requests between at least one input and at least one output. Also includes is control circuitry for routing the received transaction requests from at least one input to at least one output and responds to a barrier transaction request to maintain an ordering of at least some transaction requests with respect to said barrier transaction request within a stream of transaction requests passing along one of said at least one paths. Barrier transaction requests include an indicator of transaction requests whose ordering is to be maintained.

Barrier transactions in interconnects

Interconnect circuitry is configured to provide data routes via which at least one initiator device may access at least one recipient device, the circuitry including at least one input for receiving transaction requests; at least one output for outputting transaction requests; at least one path for transmitting the transaction requests between the input and the output. Control circuitry routes received transaction requests from the input to the output in response to a barrier transaction request. An ordering of at least some transaction requests is maintained with respect to the barrier transaction request within a stream of transaction requests passing along one of the at least one paths, by not allowing reordering of at least some of the transactions requests. The control circuitry includes a response signal generator, the response signal generator is responsive to receipt of the barrier transaction request to issue a response signal.

Reduced latency barrier transaction requests in interconnects

Interconnect circuitry for a data processing apparatus is disclosed. The interconnect circuitry is configured to provide data routes via which at least one initiator device may access at least one recipient device. The interconnect circuitry comprises: at least one input for receiving transaction requests from the initiator device(s); at least one output for outputting transaction requests to the recipient device(s); a plurality of paths for transmitting said transaction requests between the at least one input and the at least one output; wherein at least one of said transaction requests comprises a data store maintenance request requesting a data store maintenance operation to be performed on data stores within the data processing apparatus; and control circuitry for routing the received transaction requests from the at least one input to the at least one output; wherein the control circuitry is configured to respond to receipt of the data store maintenance operation by transmitting the data store maintenance operation along at least one of the plurality of paths followed by a barrier transaction request, the control circuitry being configured to maintain an ordering of at least some transaction requests with respect to the barrier transaction request within a stream of transaction requests passing along the at least one of said plurality of paths, such that at least some transaction requests subsequent to the data store maintenance request in the stream of transaction requests are held behind the data store maintenance request by the barrier transaction request.

Data store maintenance requests in interconnects

Interconnect circuitry configured to provide routes for interconnecting several initiator devices and at least one recipient device including a memory. At least one of the initiator devices has a cache for storing a local copy of a subset of data items stored in the memory. The interconnect circuitry includes: a plurality of input ports and at least one output port; a plurality of paths for transmitting the transaction requests between the inputs and the at least one output; coherency control circuitry for maintaining an order in which at least some of the transaction requests to a same data storage location proceed through the interconnect circuitry. The interconnect circuitry is configured not to control the writeback transaction requests with the coherency control circuitry, such that the writeback transaction requests proceed independently of transaction requests routed through the coherency control circuitry.

Coherency control with writeback ordering

The initiator device receives requests from and issues transaction requests to a recipient device via an interconnect. A barrier generator generates barrier transaction requests indicating to the interconnect that an ordering of some transaction requests within a stream of transaction requests passing through the interconnect should be maintained by not allowing reordering of some of the transaction requests that occur before the barrier transaction request in the stream of transaction requests with respect to the barrier transaction request. In response to a synchronize request querying progress of a subset of transaction requests, the initiator device actions any pending transaction requests within the subset of transaction request and the barrier generator generates and issues a barrier transaction request to the interconnect. In response to receiving a response to the barrier transaction request, the initiator device issues an acknowledge signal as a response to the synchronize request.

Synchronising activities of various components in a distributed system

A data processing apparatus for forming a portion of a coherent cache system comprises at least one master device for performing data processing operations, and a cache coupled to the at least one master device and arranged to store data values for access by that at least one master device when performing the data processing operations. Cache coherency circuitry is responsive to a coherency request from another portion of the coherent cache system to cause a coherency action to be taken in respect of at least one data value stored in the cache. Responsive to an indication that the coherency action has resulted in invalidation of that at least one data value in the cache, refetch control circuitry is used to initiate a refetch of that at least one data value into the cache. Such a mechanism causes the refetch of data into the cache to be triggered by the coherency action performed in response to a coherency request from another portion of the coherent cache system, rather than relying on any actions taken by the at least one master device, thereby providing a very flexible and efficient mechanism for reducing cache latency in a coherent cache system.

Apparatus and method for handling data in a cache

The present invention provides a data processing apparatus and method for managing snoop operations. The data processing apparatus has a plurality of processing units for performing data processing operations requiring access to data in shared memory, with at least two of the processing units having a cache associated therewith for storing a subset of the data for access by that processing unit. A snoop-based cache coherency protocol is employed to ensure data accessed by each processing unit is up-to-date, and when an access request is issued the cache coherency protocol is referenced in order to determine whether a snoop process is required. Snoop control storage is provided which defines a plurality of snoop schemes, each snoop scheme defining a series of snoop phases to be performed to implement the snoop process, and each snoop phase requiring a snoop operation to be performed on either a single cache or multiple caches. When a snoop process is required, a snoop unit is used to reference the snoop control storage in order to identify, having regard to one or more properties of the access request, the snoop scheme to be employed to perform the snoop process. Such an approach provides a great deal of flexibility with regards to how snoop processes are implemented, in particular allowing different snoop schemes to be used dependent on the properties of the access request in question.

Data processing apparatus and method for managing snoop operations

An integrated circuitincludes a transaction masterconnected via interconnect circuitryto a transaction slaveThe transaction slavegenerates a transfer-complete signal (R Last or B) to indicate completion of a data transfer (either a read or a write). When this transfer-complete signal has been received by the transaction masterthen the transaction mastergenerates a complete-acknowledgement signal RACK, WACK, which is passed back to the transaction slave so as to acknowledge receipt of the transfer-complete signal.

Growing community of inventors

Sheffield, United Kingdom

Christopher William Laycock