Cadence Design Systems, Inc.

Christopher William Komar

Craig Franklin Deaton

Lars Lundgren

The present disclosure relates to a method for electronic circuit design. Embodiments may include receiving, using a processor, an electronic circuit design and performing a deadlock check on the electronic circuit design using a using a linear temporal logic property and a proof engine. Embodiments may further include analyzing a counterexample associated with the electronic circuit design for a loop escape condition, wherein analyzing includes proving a cover trace of a liveness obligation. If the loop escape condition is reachable from the counterexample, embodiments may include extracting one or more events associated with the loop escape condition and adding a waiver constraint to the deadlock check to force a no deadlock outcome.

System, method, and computer program product for finding and analyzing deadlock conditions associated with the formal verification of an electronic circuit design

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Phoenix, AZ, United States of America

Christopher William Komar