Adeia Semiconductor Bonding Technologies Inc.

Applied Materials, Inc.

Avago Technologies General IP (singapore) Pte. Ltd.

Christopher Wade

Belgacem Haba

Ilyas Mohammed

Richard C Ruby

Jun Zhao

Michael Louis Frank

Ellis Chau

Wei-Shun Wang

Yaxin Wang

R Shane Fazzio

David A Feld

Sean Moran

Elaine Pao

Giles Humpston

Michael James Nystrom

Xianzhi Tao

Xiaoliang Jin

A microelectronic package includes a lower unit having a lower unit substrate with conductive features and a top and bottom surface. The lower unit includes one or more lower unit chips overly/ing the top surface of the lower unit substrate that are electrically connected to the conductive features of the lower unit substrate. The microelectronic package also includes an upper unit including an upper unit substrate having conductive features, top and bottom surfaces and a hole extending between such top and bottom surfaces. The upper unit further includes one or more upper unit chips overlying the top surface of the upper unit substrate and electrically connected to the conductive features of the upper unit substrate by connections extending within the hole. The upper unit may include an upper unit encapsulant that covers the connections of the upper unit and the one or more upper unit chips.

Microelectronic package

An electronic device. The electronic device includes a first electrode and a coating layer. The electronic device is fabricated on a substrate; the substrate has a cavity created in a top surface of the substrate; and the first electrode is electrically coupled to the substrate. The coating layer coats at least part of a substrate surface in the cavity, and the presence of the coating layer results in a mitigation of at least one parasitic leakage path between the first electrode and an additional electrode fabricated on the substrate.

Electronic device on substrate with cavity and mitigated parasitic leakage path

A method of forming a wall structure in a microelectronic assembly includes selectively depositing a flowable material on an upper surface of a first element in the microelectronic assembly, positioning a molding surface in contact with the deposited flowable material and controlling a distance between the upper surface of the first element and the molding surface with one or more objects positioned between the upper surface and the molding surface.

Method of forming a wall structure in a microelectronic assembly

The present invention provides a method of forming a ruthenium seed layer on a substrate comprising the steps of introducing a ruthenium-containing compound into a CVD apparatus; introducing oxygen into the CVD apparatus; maintaining an oxygen rich environment in the process chamber for the initial formation of a ruthenium oxide seed layer; vaporizing the ruthenium-containing compound; depositing the ruthenium oxide seed layer onto the substrate by chemical vapor deposition; and annealing the deposited ruthenium oxide seed layer in a gas ambient forming a ruthenium seed layer. Also provided is a method of depositing a ruthenium thin metal film using a metalorganic precursor onto a CVD ruthenium seed layer by metalorganic chemical vapor deposition.

CVD ruthenium seed for CVD ruthenium deposition

The present invention provides a method of depositing ruthenium films on a substrate via liquid source chemical vapor deposition wherein the source material is liquid at room temperature and utilizing process conditions such that deposition of the ruthenium films occurs at a temperature in the kinetic-limited temperature regime. Also provided is a method of depositing a thin ruthenium film on a substrate by liquid source chemical vapor deposition using bis-(ethylcyclopentadienyl) ruthenium by vaporizing the bis-(ethylcyclopentadienyl) ruthenium at a vaporization temperature of about 100-300&deg; C. to form a CVD source material gas, providing an oxygen source reactant gas and forming a thin ruthenium film on a substrate in a reaction chamber using the CVD source material gas and the oxygen source reactant gas at a substrate temperature of about 100-500&deg; C.

Chemical vapor deposition of ruthenium films for metal electrode applications

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Los Gatos, CA, United States of America

Christopher Wade