Northrop Grumman Systems Corporation

Northrop Grumman Space & Mission Systems Corporation Space Technology

Christopher W Walker

Scott A Cooper

Stuart T Linsky

Ameesh N Pandya

Ali Robert Golshan

Yen M Hoang

Ryan K Cole

John M Trippett

Marlon E Marquez

Holly C Osborne

Scott Siegrist

Yenming Chen

Meina Xu

Brandon Rigg

Armin Azizian

A transmitter for a chaos communications system employing chaotic symbol modulation that perform auto-indexing, temporal gain control, increased path diversity and sequence lock up prevention. The transmitter includes a symbol mapper that converts a series of information bits to a series of bit symbols, and a chaos modulator providing chaotic spreading modulation of the bit symbols. The chaos modulator includes a plurality of chaos generators, one for each bit symbol, providing a chaos sequence for the bit symbols. Each chaos modulator includes a RAM/ROM that provides auto-indexing where a chaos sequence output from the RAM/ROM is fed back to an input of the RAM/ROM from which a chaos sequence at a next address in the RAM/ROM is selected as the output of the modulator.

High instantaneous bandwidth auto-indexing parallelized chaotic waveform data modulator and demodulator with temporal automatic gain control, increased path diversity and sequence lock up prevention

A communications system that pseudo-randomly dithers the widths of chips that are multiplied by bit symbols for spread spectrum purposes. The system includes a first random sequence generator that generates a first sequence of random numbers at a sample rate and a decision processor responsive to the first sequence of random numbers that generates a separate command at the sample rate each time one of the random numbers exceeds a predetermined threshold. The system further includes a second random sequence generator that generates select random numbers, where the second random number generator changes the select random number each time it receives one of the commands. The system also includes a chip width processor responsive to the random numbers from the second random sequence generator, where the chip width processor selects a new set of chips each having a certain width in response to receiving each random number.

Chip dithering using permuted randomized selection sets to enhance the LPI/LPD characteristics of a waveform

A sub-sampling system that is part of a modulator in a transmitter employing a chaos based architecture and including a symbol mapper and a chaos generator. The system includes M-number of channels each receiving a sequence of chaos samples from the generator and a delay device in all of the channels except one that delay the chaos samples at different delay times. The system also includes a sub-sampler in all of the channels that receive the delayed samples, where each sub-sampler outputs every predetermined one of the chaos samples and a register in each channel each storing a predetermined number of the sub-sampled chaos samples. A selection switch responsive to the stored sub-sampled chaos samples from the registers, where the selection switch is responsive to a selection signal from the symbol mapper that selects one of the registers to output the sequences of stored sub-sampled chaos samples from the system.

Reduced complexity in generating chaotic sequences for communication systems using sub-sampling techniques

A method and system of symbol measurement and combining (SMaC) provides near-optimal performance for each user independently by relying on rapid digital beamforming with near-ideal convergence properties. This approach is also provides near-ideal performance without any knowledge of user/jammer location and adapts instantly as those locations change. An iterative joint estimation method is used to determine a covariance matrix R, and a user beamsteering vector, &#x3b1;.

Method and apparatus for symbol measurement and combining

One example includes a rate detector system. The rate detector system includes a plurality of energy detectors configured to receive an input signal and to filter separate respective frequency bands associated with the input signal to generate separate respective energy profiles. The system also includes an energy processing component configured to determine a symbol rate of the input signal based on a statistical evaluation of a ratio of the separate respective energy profiles.

Communication signal rate detection system

A decoder of a data signal subjected to phase shifting keying (PSK) modulation uses a plurality of phase locked loops (-to-) having an inner decoder for short block codes, at least one of which is adapted to apply excess processing power to process a selected burst of the data signal, such as processing the burst with multiple initial phase/frequency error estimates. A selection circuit identifies the burst and supplies to said one of said plurality of phase-locked loops (-to-) for re-processing the bust with excess processing power. An outer Reed-Solomon block decoder (319) may be used to correct errors in the codewords from the phase locked loops and may be used in the selection of the burst by the selection circuit.

Decision directed phase locked loops (DD-PLL) with excess processing power in digital communication systems

Constellations () arranged in a concentric circle pattern provide simplified control of modulated communication. A plurality of concentric circles () with defined points () include convolutionally coded and uncoded bits. Constellation patterns having three or four concentric circles () are provided. A magnitude error for each of the points () allows for deviations during communication. The constellations () provide efficient communication using non-linear channels.

Constellation mapping for modulated communications

A decision directed phase locked loop (DD-PLL) is efficiently implemented in a communication receiver. The phase locked loop includes an enhanced block decoder inside a phase detector which takes in the baseband complex samples and the current channel phase estimate (or the tracked phase) and generates a feedback phase error term. A loop filter filters the phase error terms and a phase accumulator updates the tracked phase estimate on each iteration of the loop.

Efficient implementation of a decision directed phase locked loop (DD-PLL) for use with short block code in digital communication systems

A demodulator demodulates a modulated signal waveform in a data communication system. A phase tracking loop tracks the phase of said modulated signal waveform and having an inner block decoder configured to decode a set of vector pairs of the modulated signal waveform at a decode rate to generate associated codewords and phase estimates. A group of data symbols consisting of the first data symbols of the modulated signal waveform are run backwards through the phase tracking loop. An outer block decoder receives the associated codewords generated by said inner block decoder and utilizes and corrects only codewords associated with symbols after and including the group of data symbols consisting of the first data symbols of the modulated signal waveform.

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Rancho Palos Verdes, CA, United States of America

Christopher W Walker