Micron Technology Incorporated

Intel Corporation

Christopher W Petz

Yongjun Jeff Hu

Everett Allen McTeer

Durai Vishak Nirmal Ramaswamy

Sanket S Kelkar

Scott E Sills

John Mark Meldrim

Matthew N Rocklein

Haoyu Li

Dale Collins

Daniel Billingsley

David Ross Economy

Luca Fumagalli

Dojun Kim

Brenda D Kraus

Vassil N Antonov

Tsz Wah Chan

Clement Jacob

John David Hopkins

Jordan D Greenlee

Allen McTeer

Rita J Klein

Shuichiro Yasuda

Qian Tao

Jaydeb Goswami

Albert Liao

Kentaro Ishii

Zhe Song

Paul A Paduano

Christian George Emor

Amirhasan Nourbakhsh

An-Jen B Cheng

Sanh D Tang

Ronald Allen Weimer

Kunal Shrotri

Swapnil Lengade

Sanjeev Sapra

Beth R Cook

Tom Jibu John

Wei Yeeng Ng

Prakash Rau Mokhna Rau

Devesh Dadhich Shreeram

Richard L Elliott

Gurpreet S Lugani

Pankaj Sharma

Saurabh Keshav

Hidekazu Nobuto

Yong Mo Yang

Richard Beeler

Ke-Hung Chen

Dan Mihai Mocuta

Philip M Campbell

Tsz-Wah Chan

Toshihiko Miyashita

Dale W Collins

A DRAM capacitor comprising a first capacitor electrode configured as a container and comprising a doped titanium nitride material, a capacitor dielectric on the first capacitor electrode, and a second capacitor electrode on the capacitor dielectric. Methods of forming the DRAM capacitor are also disclosed, as are semiconductor devices and systems comprising such DRAM capacitors.

Doped titanium nitride materials for dram capacitors, and related semiconductor devices

A variety of applications can include apparatus having p-channel metal-oxide-semiconductor (PMOS) transistors and n-channel metal-oxide-semiconductor (NMOS) transistors with different metal silicide contacts. The active area of the NMOS transistor can include a first metal silicide having a first metal element, where the first metal silicide is a vertical lowest portion of a contact for the NMOS. The PMOS transistor can include a stressor source/drain region to a channel region of the PMOS transistor and a second metal silicide directly contacting the stressor source/drain region without containing the first metal element. The process flow to form the PMOS and NMOS transistors can enable making simultaneous contacts by a pre-silicide in the active area of the NMOS transistor, without affecting stressor source/drain regions in the PMOS transistor. The process flow and resulting structures for PMOS transistors and NMOS transistors can be used in various integrated circuits and devices.

Active area salicidation for NMOS and PMOS devices

A microelectronic device includes a first conductive structure, a barrier structure, a conductive liner structure, and a second conductive structure. The first conductive structure is within a first filled opening in a first dielectric structure. The barrier structure is within the first filled opening in the first dielectric structure and vertically overlies the first conductive structure. The conductive liner structure is on the barrier structure and is within a second filled opening in a second dielectric structure vertically overlying the first dielectric structure. The second conductive structure vertically overlies and is horizontally surrounded by the conductive liner structure within the second filled opening in the second dielectric structure. Memory devices, electronic systems, and methods of forming microelectronic devices are also described.

Microelectronic devices, memory devices, and electronic systems

Some embodiments include an integrated assembly having capacitor-contact-regions. Metal-containing interconnects are coupled with the capacitor-contact-regions. A first insulative material is between the metal-containing interconnects. A second insulative material is over the first insulative material. A third insulative material is over the second insulative material. First capacitor electrodes extend through the second and third insulative materials and are coupled with the metal-containing interconnects. Fourth insulative material is adjacent the first capacitor electrodes. Capacitor plate electrodes are adjacent the fourth insulative material and are spaced from the first capacitor electrodes by the fourth insulative material. Some embodiments include methods of forming integrated assemblies.

Methods of utilizing etch-stop material during fabrication of capacitors, integrated assemblies comprising capacitors

Apparatuses, methods, and systems related to electrode formation are described. A first portion of a top electrode is formed over a dielectric material of a storage node. A metal oxide is formed over the first portion of the electrode. A second portion of the electrode is formed over the metal oxide.

Electrode formation

A ferroelectric capacitor comprises two conductive capacitor electrodes having ferroelectric material there-between. At least one of the capacitor electrodes comprise MSiO, where 'M' is at least one of Ru, Ti, Ta, Co, Pt, Ir, Os, Mo, V, W, Sr, Re, Rh, Pd, La, Zn, In, Sig, and Nb, Other aspects, including method, are disclosed.

Ferroelectric capacitor, a ferroelectric memory cell, an array of ferroelectric memory cells, and a method of forming a ferroelectric capacitor

A semiconductor device comprises a semiconductor material extending through a stack of alternating levels of a conductive material and an insulative material, and a material comprising cerium oxide and at least another oxide adjacent to the semiconductor material. Related electronic systems and methods are also disclosed.

Semiconductor devices and electronic systems including an etch stop material, and related methods

A material deposition system comprises a dopant source containing at least one dopant precursor material, an inert gas source containing at least one noble gas, and a physical vapor deposition apparatus in selective fluid communication with the dopant source and the inert gas source. The physical vapor deposition apparatus comprises a housing structure, a target electrode, and a substrate holder. The housing structure is configured and positioned to receive at least one feed fluid stream comprising the at least one dopant precursor material and the at least one noble gas. The target electrode is within the housing structure and is in electrical communication with a signal generator. The substrate holder is within the housing structure and is spaced apart from the target electrode. A method of forming a microelectronic device, a microelectronic device, a memory device, and an electronic system are also described.

Material deposition systems, and related methods

Methods of forming microelectronic devices, and related microelectronic devices, memory devices, and electronic systems

An apparatus comprising a memory array comprising access lines. Each of the access lines comprises an insulating material adjacent a bottom surface and sidewalls of a base material, a first conductive material adjacent the insulating material, a second conductive material adjacent the first conductive material, and a barrier material between the first conductive material and the second conductive material. The barrier material is configured to suppress migration of reactive species from the second conductive material. Methods of forming the apparatus and electronic systems are also disclosed.

Apparatus including barrier materials within access line structures, and related methods and electronic systems

Doped titanium nitride materials for DRAM capacitors, and related semiconductor devices, systems, and methods

Methods, apparatuses, and systems related to forming a barrier material on an electrode are described. An example method includes forming a top electrode of a storage node on a dielectric material in a semiconductor fabrication sequence and forming, in-situ in a semiconductor fabrication apparatus, a barrier material on the top electrode to reduce damage to the dielectric material when ex-situ of the semiconductor fabrication apparatus.

Forming a barrier material on an electrode

Methods, apparatuses, and systems related to forming a barrier material between an electrode and a dielectric material are described. An example method includes forming a dielectric material on a bottom electrode material of a storage node in a semiconductor fabrication process. The method further includes forming a barrier material on the dielectric material to reduce oxygen vacancies in the dielectric material. The method further includes forming a top electrode on the barrier material.

Electrode/dielectric barrier material formation and structures

Devices and systems having a diffusion barrier for limiting diffusion of a phase change material including an electrode, a phase change material electrically coupled to the electrode, and a carbon and TiN (C:TiN) diffusion barrier disposed between the electrode and the phase change material to limit diffusion of the phase change material are disclosed and described.

Laminate diffusion barriers and related devices and methods

A method of forming an apparatus comprises forming a first metal nitride material over an upper surface of a conductive material within an opening extending through at least one dielectric material through a non-conformal deposition process. A second metal nitride material is formed over an upper surface of the first metal nitride material and side surfaces of the at least one dielectric material partially defining boundaries of the opening through a conformal deposition process. A conductive structure is formed over surfaces of the second metal nitride material within the opening. Apparatuses and electronic systems are also described.

Devices, methods of forming a device, and memory devices

Growing community of inventors

Boise, ID, United States of America

Christopher W Petz